diff mbox series

[5/8] Revert "RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740"

Message ID 20210326205803.157027-6-xnox@ubuntu.com
State New
Headers show
Series Fixup old unmatched patches, thus fix l2 cache | expand

Commit Message

Dimitri John Ledkov March 26, 2021, 8:58 p.m. UTC 
This reverts commit 5063de1bbb516d06347285ad2a65cd8a23c6e75a.

Signed-off-by: Dimitri John Ledkov <xnox@ubuntu.com>
---
 drivers/soc/sifive/sifive_l2_cache.c | 49 ++++------------------------
 1 file changed, 6 insertions(+), 43 deletions(-)
diff mbox series

Patch

diff --git a/drivers/soc/sifive/sifive_l2_cache.c b/drivers/soc/sifive/sifive_l2_cache.c
index 4e5e8411fbdd..44d7e1951da3 100644
--- a/drivers/soc/sifive/sifive_l2_cache.c
+++ b/drivers/soc/sifive/sifive_l2_cache.c
@@ -17,10 +17,6 @@ 
 #define SIFIVE_L2_DIRECCFIX_HIGH 0x104
 #define SIFIVE_L2_DIRECCFIX_COUNT 0x108
 
-#define SIFIVE_L2_DIRECCFAIL_LOW 0x120
-#define SIFIVE_L2_DIRECCFAIL_HIGH 0x124
-#define SIFIVE_L2_DIRECCFAIL_COUNT 0x128
-
 #define SIFIVE_L2_DATECCFIX_LOW 0x140
 #define SIFIVE_L2_DATECCFIX_HIGH 0x144
 #define SIFIVE_L2_DATECCFIX_COUNT 0x148
@@ -33,7 +29,7 @@ 
 #define SIFIVE_L2_WAYENABLE 0x08
 #define SIFIVE_L2_ECCINJECTERR 0x40
 
-#define SIFIVE_L2_MAX_ECCINTR 4
+#define SIFIVE_L2_MAX_ECCINTR 3
 
 static void __iomem *l2_base;
 static int g_irq[SIFIVE_L2_MAX_ECCINTR];
@@ -41,7 +37,6 @@  static struct riscv_cacheinfo_ops l2_cache_ops;
 
 enum {
 	DIR_CORR = 0,
-	DIR_UNCORR,
 	DATA_CORR,
 	DATA_UNCORR,
 };
@@ -98,7 +93,6 @@  static void l2_config_read(void)
 
 static const struct of_device_id sifive_l2_ids[] = {
 	{ .compatible = "sifive,fu540-c000-ccache" },
-	{ .compatible = "sifive,fu740-c000-ccache" },
 	{ /* end of table */ },
 };
 
@@ -161,15 +155,6 @@  static irqreturn_t l2_int_handler(int irq, void *device)
 		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_CE,
 					   "DirECCFix");
 	}
-	if (irq == g_irq[DIR_UNCORR]) {
-		add_h = readl(l2_base + SIFIVE_L2_DIRECCFAIL_HIGH);
-		add_l = readl(l2_base + SIFIVE_L2_DIRECCFAIL_LOW);
-		/* Reading this register clears the DirFail interrupt sig */
-		readl(l2_base + SIFIVE_L2_DIRECCFAIL_COUNT);
-		atomic_notifier_call_chain(&l2_err_chain, SIFIVE_L2_ERR_TYPE_UE,
-					   "DirECCFail");
-		panic("L2CACHE: DirFail @ 0x%08X.%08X\n", add_h, add_l);
-	}
 	if (irq == g_irq[DATA_CORR]) {
 		add_h = readl(l2_base + SIFIVE_L2_DATECCFIX_HIGH);
 		add_l = readl(l2_base + SIFIVE_L2_DATECCFIX_LOW);
@@ -194,9 +179,9 @@  static irqreturn_t l2_int_handler(int irq, void *device)
 
 static int __init sifive_l2_init(void)
 {
-	int i, k, rc, intr_num, offset = 0;
 	struct device_node *np;
 	struct resource res;
+	int i, rc;
 
 	np = of_find_matching_node(NULL, sifive_l2_ids);
 	if (!np)
@@ -209,33 +194,11 @@  static int __init sifive_l2_init(void)
 	if (!l2_base)
 		return -ENOMEM;
 
-	intr_num = of_property_count_u32_elems(np, "interrupts");
-	if (!intr_num) {
-		pr_err("L2CACHE: no interrupts property\n");
-		return -ENODEV;
-	}
-
-	/*
-	 * Only FU540 have 3 interrupts. Rest all other variants have
-	 * 4 interrupts (+dirfail). Therefore offset is required to skip
-	 * 'dirfail' interrupt entry in case of FU540
-	 */
-	if (of_device_is_compatible(np, "sifive,fu540-c000-ccache"))
-		offset = 1;
-
-	g_irq[0] = irq_of_parse_and_map(np, 0);
-	rc = request_irq(g_irq[0], l2_int_handler, 0, "l2_ecc", NULL);
-	if (rc) {
-		pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[0]);
-		return rc;
-	}
-
-	for (i = 1; i < intr_num; i++) {
-		k = i + offset;
-		g_irq[k] = irq_of_parse_and_map(np, i);
-		rc = request_irq(g_irq[k], l2_int_handler, 0, "l2_ecc", NULL);
+	for (i = 0; i < SIFIVE_L2_MAX_ECCINTR; i++) {
+		g_irq[i] = irq_of_parse_and_map(np, i);
+		rc = request_irq(g_irq[i], l2_int_handler, 0, "l2_ecc", NULL);
 		if (rc) {
-			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[k]);
+			pr_err("L2CACHE: Could not request IRQ %d\n", g_irq[i]);
 			return rc;
 		}
 	}