diff mbox series

[SRU,B] UBUNTU: SAUCE: Move SSBS snippet from arm64_elf_hwcaps to arm64_features

Message ID 20210122052925.38477-1-ike.pan@canonical.com
State New
Headers show
Series [SRU,B] UBUNTU: SAUCE: Move SSBS snippet from arm64_elf_hwcaps to arm64_features | expand

Commit Message

Ike Panhc Jan. 22, 2021, 5:29 a.m. UTC
BugLink: https://launchpad.net/bugs/1911376

The SSBS snippet in arch/arm64/kernel/cpufeature.c shall be in
arm64_features not in arm64_elf_hwcaps. It seems when we backport
patch d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise
to userspace") and put it in wrong place.

This problem does not affect ubuntu-focal kernel.

Signed-off-by: Ike Panhc <ike.pan@canonical.com>
---
 arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Comments

Thadeu Lima de Souza Cascardo Jan. 28, 2021, 12:52 p.m. UTC | #1
On Fri, Jan 22, 2021 at 01:29:25PM +0800, Ike Panhc wrote:
> BugLink: https://launchpad.net/bugs/1911376
> 
> The SSBS snippet in arch/arm64/kernel/cpufeature.c shall be in
> arm64_features not in arm64_elf_hwcaps. It seems when we backport
> patch d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise
> to userspace") and put it in wrong place.
> 
> This problem does not affect ubuntu-focal kernel.
> 
> Signed-off-by: Ike Panhc <ike.pan@canonical.com>
> ---
>  arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 63d44403d781..cbc61d9240a9 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1194,6 +1194,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.cpu_enable = cpu_clear_disr,
>  	},
>  #endif /* CONFIG_ARM64_RAS_EXTN */
> +#ifdef CONFIG_ARM64_SSBD
> +	{
> +		.desc = "Speculative Store Bypassing Safe (SSBS)",
> +		.capability = ARM64_SSBS,
> +		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64PFR1_EL1,
> +		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> +		.sign = FTR_UNSIGNED,
> +		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> +		.cpu_enable = cpu_enable_ssbs,
> +	},
> +#endif
>  	{},
>  };
>  
> @@ -1252,19 +1265,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
>  	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
>  #ifdef CONFIG_ARM64_SVE
>  	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
> -#endif
> -#ifdef CONFIG_ARM64_SSBD
> -	{
> -		.desc = "Speculative Store Bypassing Safe (SSBS)",
> -		.capability = ARM64_SSBS,
> -		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> -		.matches = has_cpuid_feature,
> -		.sys_reg = SYS_ID_AA64PFR1_EL1,
> -		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> -		.sign = FTR_UNSIGNED,
> -		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> -		.cpu_enable = cpu_enable_ssbs,
> -	},
>  #endif
>  	{},
>  };
> -- 
> 2.25.1

Thanks for catching this. Indeed, our backport was wrong, and applying this fix
makes it closer to 4.14.217.

Acked-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
Stefan Bader Jan. 29, 2021, 9:15 a.m. UTC | #2
On 22.01.21 06:29, Ike Panhc wrote:
> BugLink: https://launchpad.net/bugs/1911376
> 
> The SSBS snippet in arch/arm64/kernel/cpufeature.c shall be in
> arm64_features not in arm64_elf_hwcaps. It seems when we backport
> patch d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise
> to userspace") and put it in wrong place.
> 
> This problem does not affect ubuntu-focal kernel.
> 
> Signed-off-by: Ike Panhc <ike.pan@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
> ---
>  arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 63d44403d781..cbc61d9240a9 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1194,6 +1194,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.cpu_enable = cpu_clear_disr,
>  	},
>  #endif /* CONFIG_ARM64_RAS_EXTN */
> +#ifdef CONFIG_ARM64_SSBD
> +	{
> +		.desc = "Speculative Store Bypassing Safe (SSBS)",
> +		.capability = ARM64_SSBS,
> +		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64PFR1_EL1,
> +		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> +		.sign = FTR_UNSIGNED,
> +		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> +		.cpu_enable = cpu_enable_ssbs,
> +	},
> +#endif
>  	{},
>  };
>  
> @@ -1252,19 +1265,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
>  	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
>  #ifdef CONFIG_ARM64_SVE
>  	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
> -#endif
> -#ifdef CONFIG_ARM64_SSBD
> -	{
> -		.desc = "Speculative Store Bypassing Safe (SSBS)",
> -		.capability = ARM64_SSBS,
> -		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> -		.matches = has_cpuid_feature,
> -		.sys_reg = SYS_ID_AA64PFR1_EL1,
> -		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> -		.sign = FTR_UNSIGNED,
> -		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> -		.cpu_enable = cpu_enable_ssbs,
> -	},
>  #endif
>  	{},
>  };
>
William Breathitt Gray Feb. 8, 2021, 2:19 p.m. UTC | #3
On Fri, Jan 22, 2021 at 01:29:25PM +0800, Ike Panhc wrote:
> BugLink: https://launchpad.net/bugs/1911376
> 
> The SSBS snippet in arch/arm64/kernel/cpufeature.c shall be in
> arm64_features not in arm64_elf_hwcaps. It seems when we backport
> patch d71be2b6c0e1 ("arm64: cpufeature: Detect SSBS and advertise
> to userspace") and put it in wrong place.
> 
> This problem does not affect ubuntu-focal kernel.
> 
> Signed-off-by: Ike Panhc <ike.pan@canonical.com>
> ---
>  arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 63d44403d781..cbc61d9240a9 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1194,6 +1194,19 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
>  		.cpu_enable = cpu_clear_disr,
>  	},
>  #endif /* CONFIG_ARM64_RAS_EXTN */
> +#ifdef CONFIG_ARM64_SSBD
> +	{
> +		.desc = "Speculative Store Bypassing Safe (SSBS)",
> +		.capability = ARM64_SSBS,
> +		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> +		.matches = has_cpuid_feature,
> +		.sys_reg = SYS_ID_AA64PFR1_EL1,
> +		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> +		.sign = FTR_UNSIGNED,
> +		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> +		.cpu_enable = cpu_enable_ssbs,
> +	},
> +#endif
>  	{},
>  };
>  
> @@ -1252,19 +1265,6 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
>  	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
>  #ifdef CONFIG_ARM64_SVE
>  	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
> -#endif
> -#ifdef CONFIG_ARM64_SSBD
> -	{
> -		.desc = "Speculative Store Bypassing Safe (SSBS)",
> -		.capability = ARM64_SSBS,
> -		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> -		.matches = has_cpuid_feature,
> -		.sys_reg = SYS_ID_AA64PFR1_EL1,
> -		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
> -		.sign = FTR_UNSIGNED,
> -		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
> -		.cpu_enable = cpu_enable_ssbs,
> -	},
>  #endif
>  	{},
>  };
> -- 
> 2.25.1
> 
> 
> -- 
> kernel-team mailing list
> kernel-team@lists.ubuntu.com
> https://lists.ubuntu.com/mailman/listinfo/kernel-team

Applied to bionic:linux/master-next.

William Breathitt Gray <william.gray@canonical.com>
diff mbox series

Patch

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 63d44403d781..cbc61d9240a9 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1194,6 +1194,19 @@  static const struct arm64_cpu_capabilities arm64_features[] = {
 		.cpu_enable = cpu_clear_disr,
 	},
 #endif /* CONFIG_ARM64_RAS_EXTN */
+#ifdef CONFIG_ARM64_SSBD
+	{
+		.desc = "Speculative Store Bypassing Safe (SSBS)",
+		.capability = ARM64_SSBS,
+		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
+		.matches = has_cpuid_feature,
+		.sys_reg = SYS_ID_AA64PFR1_EL1,
+		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
+		.sign = FTR_UNSIGNED,
+		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
+		.cpu_enable = cpu_enable_ssbs,
+	},
+#endif
 	{},
 };
 
@@ -1252,19 +1265,6 @@  static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
 	HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, HWCAP_SSBS),
 #ifdef CONFIG_ARM64_SVE
 	HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
-#endif
-#ifdef CONFIG_ARM64_SSBD
-	{
-		.desc = "Speculative Store Bypassing Safe (SSBS)",
-		.capability = ARM64_SSBS,
-		.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
-		.matches = has_cpuid_feature,
-		.sys_reg = SYS_ID_AA64PFR1_EL1,
-		.field_pos = ID_AA64PFR1_SSBS_SHIFT,
-		.sign = FTR_UNSIGNED,
-		.min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
-		.cpu_enable = cpu_enable_ssbs,
-	},
 #endif
 	{},
 };