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[Raring,3/3] PCI: Support PCIe Capability Slot registers only for ports with slots

Message ID 1384933400-25393-3-git-send-email-adam.lee@canonical.com
State New
Headers show

Commit Message

Adam Lee Nov. 20, 2013, 7:43 a.m. UTC 
From: Bjorn Helgaas <bhelgaas@google.com>

BugLink: http://bugs.launchpad.net/bugs/1252987

Previously we allowed callers to access Slot Capabilities, Status, and
Control for Root Ports even if the Root Port did not implement a slot.
This seems dubious because the spec only requires these registers if a
slot is implemented.

It's true that even Root Ports without slots must have *space* for these
slot registers, because the Root Capabilities, Status, and Control
registers are after the slot registers in the capability.  However,
for a v1 PCIe Capability, the *semantics* of the slot registers are
undefined unless a slot is implemented.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-By: Jiang Liu <jiang.liu@huawei.com>
(backported from commit 6d3a1741f1e648cfbd5a0cc94477a0d5004c6f5e)
Signed-off-by: Adam Lee <adam.lee@canonical.com>

Conflicts:
	drivers/pci/access.c
---
 drivers/pci/access.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
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Patch

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 85df60f..400785a 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -497,9 +497,9 @@  static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
 {
 	int type = pci_pcie_type(dev);
 
-	return type == PCI_EXP_TYPE_ROOT_PORT ||
-	       (type == PCI_EXP_TYPE_DOWNSTREAM &&
-		dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT);
+	return (type == PCI_EXP_TYPE_ROOT_PORT ||
+		type == PCI_EXP_TYPE_DOWNSTREAM) &&
+		dev->pcie_flags_reg & PCI_EXP_FLAGS_SLOT;
 }
 
 static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)