Message ID | 1315323393-3288-1-git-send-email-robert.hooker@canonical.com |
---|---|
State | New |
Headers | show |
This is a commit in 3.1 that fixes a frequent GPU hang on ivybridge and is not yet in stable. It adds a few new register defines, then uses them only on GEN7 which is ivybridge so it does not affect any other generation making it safe to apply. It is a clean cherry-pick into oneiric and was tested on an ivybridge machine.
On 09/06/2011 08:36 AM, Robert Hooker wrote: > From: Jesse Barnes<jbarnes@virtuousgeek.org> > > Prior to Ivybridge, the GFX_MODE would default to 0x800, meaning that > MI_FLUSH would flush the TLBs in addition to the rest of the caches > indicated in the MI_FLUSH command. However starting with Ivybridge, the > register defaults to 0x2800 out of reset, meaning that to invalidate the > TLB we need to use PIPE_CONTROL. Since we're not doing that yet, go > back to the old default so things work. > > v2: don't forget to actually *clear* the new bit > > Reviewed-by: Eric Anholt<eric@anholt.net> > Reviewed-by: Chris Wilson<chris@chris-wilson.co.uk> > Tested-by: Kenneth Graunke<kenneth@whitecape.org> > Signed-off-by: Jesse Barnes<jbarnes@virtuousgeek.org> > (cherry picked from commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f) > > Signed-off-by: Robert Hooker<robert.hooker@canonical.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++++ > 2 files changed, 8 insertions(+), 0 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5d5def7..2c34d07 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -367,6 +367,7 @@ > # define MI_FLUSH_ENABLE (1<< 11) > > #define GFX_MODE 0x02520 > +#define GFX_MODE_GEN7 0x0229c > #define GFX_RUN_LIST_ENABLE (1<<15) > #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) > #define GFX_SURFACE_FAULT_ENABLE (1<<12) > @@ -374,6 +375,9 @@ > #define GFX_PSMI_GRANULARITY (1<<10) > #define GFX_PPGTT_ENABLE (1<<9) > > +#define GFX_MODE_ENABLE(bit) (((bit)<< 16) | (bit)) > +#define GFX_MODE_DISABLE(bit) (((bit)<< 16) | (0)) > + > #define SCPD0 0x0209c /* 915+ only */ > #define IER 0x020a0 > #define IIR 0x020a4 > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 1f61fc7..996264e 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -289,6 +289,10 @@ static int init_render_ring(struct intel_ring_buffer *ring) > if (IS_GEN6(dev) || IS_GEN7(dev)) > mode |= MI_FLUSH_ENABLE<< 16 | MI_FLUSH_ENABLE; > I915_WRITE(MI_MODE, mode); > + if (IS_GEN7(dev)) > + I915_WRITE(GFX_MODE_GEN7, > + GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | > + GFX_MODE_ENABLE(GFX_REPLAY_MODE)); > } > > if (INTEL_INFO(dev)->gen>= 6) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5d5def7..2c34d07 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -367,6 +367,7 @@ # define MI_FLUSH_ENABLE (1 << 11) #define GFX_MODE 0x02520 +#define GFX_MODE_GEN7 0x0229c #define GFX_RUN_LIST_ENABLE (1<<15) #define GFX_TLB_INVALIDATE_ALWAYS (1<<13) #define GFX_SURFACE_FAULT_ENABLE (1<<12) @@ -374,6 +375,9 @@ #define GFX_PSMI_GRANULARITY (1<<10) #define GFX_PPGTT_ENABLE (1<<9) +#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit)) +#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0)) + #define SCPD0 0x0209c /* 915+ only */ #define IER 0x020a0 #define IIR 0x020a4 diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 1f61fc7..996264e 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -289,6 +289,10 @@ static int init_render_ring(struct intel_ring_buffer *ring) if (IS_GEN6(dev) || IS_GEN7(dev)) mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; I915_WRITE(MI_MODE, mode); + if (IS_GEN7(dev)) + I915_WRITE(GFX_MODE_GEN7, + GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | + GFX_MODE_ENABLE(GFX_REPLAY_MODE)); } if (INTEL_INFO(dev)->gen >= 6) {