@@ -15,9 +15,7 @@ obj-y += clock.o
obj-y += sys_info.o
obj-y += prcm-regs.o
obj-y += hw_data.o
-ifdef CONFIG_XPL_BUILD
obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o
-endif
obj-$(CONFIG_DRIVER_TI_EMAC) += emac.o
obj-$(CONFIG_EMIF4) += emif4.o
@@ -146,10 +146,10 @@ static void do_sdrc_init(u32 cs, u32 early)
* then set cs_cfg to the appropriate value then try and
* setup CS1.
*/
-#ifdef CONFIG_XPL_BUILD
+
/* set/modify board-specific timings */
get_board_mem_timings(&timings);
-#endif
+#if IS_ENABLED(CONFIG_XPL_BUILD)
if (early) {
/* reset sdrc controller */
writel(SOFTRESET, &sdrc_base->sysconfig);
@@ -166,14 +166,13 @@ static void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
sdelay(0x20000);
-#ifdef CONFIG_XPL_BUILD
- write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
- make_cs1_contiguous();
- write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
-#endif
-
}
+#endif
+ write_sdrc_timings(CS0, sdrc_actim_base0, &timings);
+ make_cs1_contiguous();
+ write_sdrc_timings(CS1, sdrc_actim_base1, &timings);
+#if IS_ENABLED(CONFIG_XPL_BUILD)
/*
* If we aren't using SPL we have been loaded by some
* other means which may not have correctly initialized
@@ -188,6 +187,7 @@ static void do_sdrc_init(u32 cs, u32 early)
timings.mr = readl(&sdrc_base->cs[CS0].mr);
write_sdrc_timings(cs, sdrc_actim_base1, &timings);
}
+#endif
}
/*
@@ -230,6 +230,7 @@ int dram_init_banksize(void)
return 0;
}
+#if IS_ENABLED(CONFIG_XPL_BUILD)
/*
* omap3_mem_init -
* - Init the sdrc chip,
@@ -240,3 +241,4 @@ void omap3_mem_init(void)
/* only init up first bank here */
do_sdrc_init(CS0, EARLY_INIT);
}
+#endif
@@ -24,7 +24,9 @@
#endif
#include <twl4030.h>
#include <asm/global_data.h>
+#if (IS_ENABLED(CONFIG_MTD_RAW_NAND))
#include <linux/mtd/rawnand.h>
+#endif
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <i2c.h>
@@ -70,6 +72,11 @@ static struct {
char env_setting[64];
} expansion_config;
+#if (IS_ENABLED(CONFIG_SPL_OMAP3_ID_NAND))
+static int mfr_id;
+static int pop_id;
+#endif
+
/*
* Routine: board_init
* Description: Early hardware init.
@@ -135,7 +142,6 @@ static int get_board_revision(void)
return revision;
}
-#if (IS_ENABLED(CONFIG_SPL_BUILD))
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
@@ -143,55 +149,46 @@ static int get_board_revision(void)
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
- int pop_mfr, pop_id;
-
- /*
- * We need to identify what PoP memory is on the board so that
- * we know what timings to use. If we can't identify it then
- * we know it's an xM. To map the ID values please see nand_ids.c
- */
- identify_nand_chip(&pop_mfr, &pop_id);
-
timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_C4:
- if (pop_mfr == NAND_MFR_STMICRO && pop_id == 0xba) {
+#if (IS_ENABLED(CONFIG_SPL_OMAP3_ID_NAND))
+ /*
+ * We need to identify what PoP memory is on the board to know
+ * what timings to use. To map the ID values please see nand_ids.c
+ */
+ identify_nand_chip(&mfr_id, &pop_id);
+
+ if (mfr_id == NAND_MFR_STMICRO && pop_id == 0xba) {
/* 512MB DDR */
timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
timings->ctrla = NUMONYX_V_ACTIMA_165;
timings->ctrlb = NUMONYX_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHZ;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xba) {
+ }
+ if (mfr_id == NAND_MFR_MICRON && pop_id == 0xba) {
/* Beagleboard Rev C4, 512MB Nand/256MB DDR*/
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHZ;
- break;
- } else if (pop_mfr == NAND_MFR_MICRON && pop_id == 0xbc) {
+ }
+ if (mfr_id == NAND_MFR_MICRON && pop_id == 0xbc) {
/* Beagleboard Rev C5, 256MB DDR */
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHZ;
- break;
}
+ break;
+#endif
case REVISION_XM_AB:
case REVISION_XM_C:
- if (pop_mfr == 0) {
- /* 256MB DDR */
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHZ;
- } else {
- /* 512MB DDR */
- timings->mcfg = NUMONYX_V_MCFG_165(512 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHZ;
- }
+ /* 512MB DDR */
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHZ;
break;
default:
/* Assume 128MB and Micron/165MHz timings to be safe */
@@ -201,7 +198,6 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHZ;
}
}
-#endif
/*
* Routine: get_expansion_id
GPIOs are read to determine which BeagleBoard variant we are running on. It also affects the memory timings for LPDDR. The GPIO lines are not valid for SPL until we are attempting the first boot device. The GPIO lines need to be checked again in U-Boot because they were not valid early on in SPL. The board and LPDDR timings are now correct. Signed-off-by: Nevets Llih <omapbsf@protonmail.com> --- arch/arm/mach-omap2/omap3/Makefile | 2 -- arch/arm/mach-omap2/omap3/sdrc.c | 18 +++++----- board/beagle/beagle/beagle.c | 56 ++++++++++++++---------------- 3 files changed, 36 insertions(+), 40 deletions(-)