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[U-Boot,9/9] arm64: zynqmp: Change the spi-rx-bus-width property to x1

Message ID f91815806809c61bf65fb93e8d474aaa8cc3959a.1550073256.git.michal.simek@xilinx.com
State Accepted
Commit 053d4bd4727185f292a0bb2ac080c8c6ae794cbe
Delegated to: Michal Simek
Headers show
Series xilinx: dts: Update various DT files | expand

Commit Message

Michal Simek Feb. 13, 2019, 3:54 p.m. UTC 
From: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>

As per the zc1275 design x1 mode is enabled so changing the
spi-rx-bus-width property to x1.

Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 arch/arm/dts/zynqmp-zc1275-revB.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
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Patch

diff --git a/arch/arm/dts/zynqmp-zc1275-revB.dts b/arch/arm/dts/zynqmp-zc1275-revB.dts
index 027ff83562f8..d7685d2e6d82 100644
--- a/arch/arm/dts/zynqmp-zc1275-revB.dts
+++ b/arch/arm/dts/zynqmp-zc1275-revB.dts
@@ -62,7 +62,7 @@ 
 		#size-cells = <1>;
 		reg = <0x0>;
 		spi-tx-bus-width = <1>;
-		spi-rx-bus-width = <4>;
+		spi-rx-bus-width = <1>;
 		spi-max-frequency = <108000000>; /* Based on DC1 spec */
 		partition@qspi-fsbl-uboot { /* for testing purpose */
 			label = "qspi-fsbl-uboot";