diff mbox series

[U-Boot,v2,3/4] arm64: versal: Rename versal_pm_request to xilinx_pm_request

Message ID f2087f76395833693b7774ec630a1b99bf3e7a25.1571053509.git.michal.simek@xilinx.com
State Accepted
Commit 6596270ecb5d74d5f997da0daa728e06d1f47029
Delegated to: Michal Simek
Headers show
Series xilinx: firmware: Synchronization firmware functions | expand

Commit Message

Michal Simek Oct. 14, 2019, 11:45 a.m. UTC 
Use generic name instead of Versal specific because this should be also
used on ZynqMP.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

Changes in v2: None

 drivers/clk/clk_versal.c           | 14 +++++++-------
 drivers/firmware/firmware-zynqmp.c |  2 +-
 drivers/fpga/versalpl.c            |  2 +-
 include/zynqmp_firmware.h          |  2 +-
 4 files changed, 10 insertions(+), 10 deletions(-)
diff mbox series

Patch

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index e0fa661be9e0..7e97b0c4bf3a 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -363,7 +363,7 @@  static u32 versal_clock_get_div(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	u32 div;
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	div = ret_payload[1];
 
 	return div;
@@ -373,7 +373,7 @@  static u32 versal_clock_set_div(u32 clk_id, u32 div)
 {
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 
-	versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
 
 	return div;
 }
@@ -383,7 +383,7 @@  static u64 versal_clock_ref(u32 clk_id)
 	u32 ret_payload[PAYLOAD_ARG_CNT];
 	int ref;
 
-	versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
 	ref = ret_payload[0];
 	if (!(ref & 1))
 		return ref_clk;
@@ -402,7 +402,7 @@  static u64 versal_clock_get_pll_rate(u32 clk_id)
 	u32 parent_rate, parent_id;
 	u32 id = clk_id & 0xFFF;
 
-	versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
 	res = ret_payload[1];
 	if (!res) {
 		printf("0%x PLL not enabled\n", clk_id);
@@ -412,9 +412,9 @@  static u64 versal_clock_get_pll_rate(u32 clk_id)
 	parent_id = clock[clock[id].parent[0].id].clk_id;
 	parent_rate = versal_clock_ref(parent_id);
 
-	versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
 	fbdiv = ret_payload[1];
-	versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
+	xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
 	frac = ret_payload[1];
 
 	freq = (fbdiv * parent_rate) >> (1 << frac);
@@ -441,7 +441,7 @@  static u32 versal_clock_get_parentid(u32 clk_id)
 	u32 id = clk_id & 0xFFF;
 
 	if (versal_clock_mux(clk_id)) {
-		versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
+		xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
 				  ret_payload);
 		parent_id = ret_payload[1];
 	}
diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c
index 840c68d45a1a..d11740ac772d 100644
--- a/drivers/firmware/firmware-zynqmp.c
+++ b/drivers/firmware/firmware-zynqmp.c
@@ -176,7 +176,7 @@  int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
 	return regs.regs[0];
 }
 
-int __maybe_unused versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 				     u32 arg3, u32 *ret_payload)
 {
 	return invoke_smc(PM_SIP_SVC | api_id, arg0, arg1, arg2, arg3,
diff --git a/drivers/fpga/versalpl.c b/drivers/fpga/versalpl.c
index 8337b8306d76..4bcc2132432b 100644
--- a/drivers/fpga/versalpl.c
+++ b/drivers/fpga/versalpl.c
@@ -39,7 +39,7 @@  static int versal_load(xilinx_desc *desc, const void *buf, size_t bsize,
 	buf_lo = lower_32_bits(bin_buf);
 	buf_hi = upper_32_bits(bin_buf);
 
-	ret = versal_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
+	ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo,
 				buf_hi, 0, ret_payload);
 	if (ret)
 		puts("PL FPGA LOAD fail\n");
diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h
index 088ba30e0bb8..84090208e50c 100644
--- a/include/zynqmp_firmware.h
+++ b/include/zynqmp_firmware.h
@@ -83,7 +83,7 @@  unsigned int zynqmp_firmware_version(void);
 void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
 int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
 	       u32 *ret_payload);
-int versal_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
+int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2,
 		      u32 arg3, u32 *ret_payload);
 
 #endif /* _ZYNQMP_FIRMWARE_H_ */