From patchwork Tue Oct 21 12:26:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 401457 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 180C814007B for ; Tue, 21 Oct 2014 23:27:46 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 76DBFA73EF; Tue, 21 Oct 2014 14:27:44 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id raPUVvBwmILi; Tue, 21 Oct 2014 14:27:43 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 918D9A73E7; Tue, 21 Oct 2014 14:27:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7E2F9A73E7 for ; Tue, 21 Oct 2014 14:27:39 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tMl1har+doNg for ; Tue, 21 Oct 2014 14:27:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by theia.denx.de (Postfix) with ESMTPS id 1C34FA73E5 for ; Tue, 21 Oct 2014 14:27:36 +0200 (CEST) Received: from localhost.localdomain (46-140-72-82.static.cablecom.ch [46.140.72.82]) by mrelay.perfora.net (node=mreueus002) with ESMTP (Nemesis) id 0M5wTf-1Y55aT0U1Z-00xqmQ; Tue, 21 Oct 2014 14:27:12 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Tue, 21 Oct 2014 14:26:36 +0200 Message-Id: X-Mailer: git-send-email 1.9.3 In-Reply-To: References: X-Provags-ID: V02:K0:/kpeWDUtqt1ysbww2yi5LZvoyXqSAMNQWGKtnxo0v9J 4QNcvcplpaRwzrp6F4PjPe7d3IuDC3zJREFLy0wNsXlczLHOho VT5jrfgweslox/MeJNUHsRtTLiwQlH6r26hW6wBtXJULpXiTWy xB2W8dxhNxeDXfpFa15CRvj4qV0p3hnSNV4fq2QNq3Lhtkp8dq uqRJsXVfjSFfH3spdhne7/0xWbqJnCqip9CiRTl1QTYdcRPec2 yHtweB0QfseT99PP37JFapnnvdUZ9bwOPaulhXoWM0R5IgWWzs i0DdtVEkmx6dGr00ovGaEEMXbbHFLe5ISp/eP/uSk7/AIHuVqk NmX+XV1cWcQyYBVYIxGNmEpGrTg/CFFT/sGG5h+wBbRznE+fcD DrOmFRHSB5wfX8MHEO+Vi7xhb+7ye3afAfgYWDyEDcuP84dydI wAuDVEzy4cWFf2jHRvLgq7E+QMg== X-UI-Out-Filterresults: notjunk:1; Cc: Marek Vasut , York Sun , Marcel Ziswiler Subject: [U-Boot] [PATCH] e1000: fix sw fw sync on igb i210/i211 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de I finally had a look at the datasheet and spotted an additional register address difference between regular E1000 and i210/i211 chips. This patch fixes this and now successfully works on programmed i210/i211 as well as unprogrammed i211. Signed-off-by: Marcel Ziswiler --- Please note that unprogrammed i210 seem to behave slightly different and do not assert the CFG_DONE bit in the EEMNGCTL register upon PHY reset. However if this error condition is ignored then successful data transfer is possible. Due to the rather hacky nature thereof this is not addressed by my patch. BTW: What about my previous patch this one kind of bases on? [PATCH] e1000: add i211 and unprogrammed i210/i211 support drivers/net/e1000.c | 6 ++++-- drivers/net/e1000.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index b092867..798c8aa 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1112,7 +1112,10 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) if (e1000_get_hw_eeprom_semaphore(hw)) return -E1000_ERR_SWFW_SYNC; - swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); + if (hw->mac_type == e1000_igb) + swfw_sync = E1000_READ_REG(hw, I210_SW_FW_SYNC); + else + swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC); if (!(swfw_sync & (fwmask | swmask))) break; @@ -4429,7 +4432,6 @@ e1000_phy_hw_reset(struct e1000_hw *hw) if (hw->mac_type >= e1000_82571) mdelay(10); - } else { /* Read the Extended Device Control Register, assert the PHY_RESET_DIR * bit to put the PHY into reset. Then, take it out of reset. diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index b025ecc..6d110eb 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -2497,6 +2497,7 @@ struct e1000_hw { #define ICH_GFPREG_BASE_MASK 0x1FFF #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF +#define E1000_I210_SW_FW_SYNC 0x5B50 /* Software-Firmware Synchronization - RW */ #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ /* SPI EEPROM Status Register */