From patchwork Fri May 20 03:21:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1633652 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L4BqY2Tkjz9sFs for ; Fri, 20 May 2022 13:22:33 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 6178583EC4; Fri, 20 May 2022 05:22:20 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id A489183EB4; Fri, 20 May 2022 05:22:09 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D801083EA0 for ; Fri, 20 May 2022 05:22:02 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: 8adc802b83bb452795a78794b3cfac6d-20220520 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:28079198-a324-4c80-868c-daa0dd831010, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Release_Ham,AC TION:release,TS:90 X-CID-INFO: VERSION:1.1.5, REQID:28079198-a324-4c80-868c-daa0dd831010, OB:0, LOB: 0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:95,FILE:0,RULE:Spam_GS981B3D,AC TION:quarantine,TS:90 X-CID-META: VersionHash:2a19b09, CLOUDID:1709e2e2-edbf-4bd4-8a34-dfc5f7bb086d, C OID:7a873259e06a,Recheck:0,SF:28|17|19|48,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,QS:0,BEC:nil X-UUID: 8adc802b83bb452795a78794b3cfac6d-20220520 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1772272716; Fri, 20 May 2022 11:21:45 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Fri, 20 May 2022 11:21:43 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 20 May 2022 11:21:43 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 20 May 2022 11:21:43 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , "Daniel Schwierzeck" , Weijie Gao Subject: [PATCH v6 02/25] mips: add more definitions for asm/cm.h Date: Fri, 20 May 2022 11:21:39 +0800 Message-ID: X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean This patch add more definitions needed for MT7621 initialization. MT7621 needs to initialize GIC/CPC and other related parts. Reviewed-by: Daniel Schwierzeck Signed-off-by: Weijie Gao --- v6 changes: none v5 changes: none v4 changes: new --- arch/mips/include/asm/cm.h | 67 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/arch/mips/include/asm/cm.h b/arch/mips/include/asm/cm.h index 99ddbccd80..5cc8c09621 100644 --- a/arch/mips/include/asm/cm.h +++ b/arch/mips/include/asm/cm.h @@ -8,9 +8,23 @@ #define __MIPS_ASM_CM_H__ /* Global Control Register (GCR) offsets */ +#define GCR_CONFIG 0x0000 #define GCR_BASE 0x0008 #define GCR_BASE_UPPER 0x000c +#define GCR_CONTROL 0x0010 +#define GCR_ACCESS 0x0020 #define GCR_REV 0x0030 +#define GCR_GIC_BASE 0x0080 +#define GCR_CPC_BASE 0x0088 +#define GCR_REG0_BASE 0x0090 +#define GCR_REG0_MASK 0x0098 +#define GCR_REG1_BASE 0x00a0 +#define GCR_REG1_MASK 0x00a8 +#define GCR_REG2_BASE 0x00b0 +#define GCR_REG2_MASK 0x00b8 +#define GCR_REG3_BASE 0x00c0 +#define GCR_REG3_MASK 0x00c8 +#define GCR_CPC_STATUS 0x00f0 #define GCR_L2_CONFIG 0x0130 #define GCR_L2_TAG_ADDR 0x0600 #define GCR_L2_TAG_ADDR_UPPER 0x0604 @@ -19,10 +33,59 @@ #define GCR_L2_DATA 0x0610 #define GCR_L2_DATA_UPPER 0x0614 #define GCR_Cx_COHERENCE 0x2008 +#define GCR_Cx_OTHER 0x2018 +#define GCR_Cx_ID 0x2028 +#define GCR_CO_COHERENCE 0x4008 + +/* GCR_CONFIG fields */ +#define GCR_CONFIG_NUM_CLUSTERS_SHIFT 23 +#define GCR_CONFIG_NUM_CLUSTERS (0x7f << 23) +#define GCR_CONFIG_NUMIOCU_SHIFT 8 +#define GCR_CONFIG_NUMIOCU (0xff << 8) +#define GCR_CONFIG_PCORES_SHIFT 0 +#define GCR_CONFIG_PCORES (0xff << 0) + +/* GCR_BASE fields */ +#define GCR_BASE_SHIFT 15 +#define CCA_DEFAULT_OVR_SHIFT 5 +#define CCA_DEFAULT_OVR_MASK (0x7 << 5) +#define CCA_DEFAULT_OVREN (0x1 << 4) +#define CM_DEFAULT_TARGET_SHIFT 0 +#define CM_DEFAULT_TARGET_MASK (0x3 << 0) + +/* GCR_CONTROL fields */ +#define GCR_CONTROL_SYNCCTL (0x1 << 16) /* GCR_REV CM versions */ #define GCR_REV_CM3 0x0800 +/* GCR_GIC_BASE fields */ +#define GCR_GIC_BASE_ADDRMASK_SHIFT 7 +#define GCR_GIC_BASE_ADDRMASK (0x1ffffff << 7) +#define GCR_GIC_EN (0x1 << 0) + +/* GCR_CPC_BASE fields */ +#define GCR_CPC_BASE_ADDRMASK_SHIFT 15 +#define GCR_CPC_BASE_ADDRMASK (0x1ffff << 15) +#define GCR_CPC_EN (0x1 << 0) + +/* GCR_REGn_MASK fields */ +#define GCR_REGn_MASK_ADDRMASK_SHIFT 16 +#define GCR_REGn_MASK_ADDRMASK (0xffff << 16) +#define GCR_REGn_MASK_CCAOVR_SHIFT 5 +#define GCR_REGn_MASK_CCAOVR (0x7 << 5) +#define GCR_REGn_MASK_CCAOVREN (1 << 4) +#define GCR_REGn_MASK_DROPL2 (1 << 2) +#define GCR_REGn_MASK_CMTGT_SHIFT 0 +#define GCR_REGn_MASK_CMTGT (0x3 << 0) +#define GCR_REGn_MASK_CMTGT_DISABLED 0x0 +#define GCR_REGn_MASK_CMTGT_MEM 0x1 +#define GCR_REGn_MASK_CMTGT_IOCU0 0x2 +#define GCR_REGn_MASK_CMTGT_IOCU1 0x3 + +/* GCR_CPC_STATUS fields */ +#define GCR_CPC_EX (0x1 << 0) + /* GCR_L2_CONFIG fields */ #define GCR_L2_CONFIG_ASSOC_SHIFT 0 #define GCR_L2_CONFIG_ASSOC_BITS 8 @@ -36,6 +99,10 @@ #define GCR_Cx_COHERENCE_DOM_EN (0xff << 0) #define GCR_Cx_COHERENCE_EN (0x1 << 0) +/* GCR_Cx_OTHER fields */ +#define GCR_Cx_OTHER_CORENUM_SHIFT 16 +#define GCR_Cx_OTHER_CORENUM (0xffff << 16) + #ifndef __ASSEMBLY__ #include