Message ID | b5792379-986a-871f-2e24-447579d7a9ee@gmail.com |
---|---|
State | Superseded |
Delegated to: | Simon Glass |
Headers | show |
Series | [RFC,v1,1/4] drivers: use dev_read_addr_index_ptr when cast to pointer | expand |
Hi On Sat, Feb 25, 2023 at 8:19 PM Johan Jonker <jbx6244@gmail.com> wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so use devfdt_get_addr_size_index_ptr instead of > the devfdt_get_addr_size_index function in the various files > in the drivers directory that cast to a pointer. > Nice if you use more size for each line ;) > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Note: > > This is needed for a Rockchip patch serie to pass the test and > must be merged before by Rockchip maintainers: > > [PATCH v4 00/11] Fixes for Rockchip NFC driver part 1 > https://lore.kernel.org/u-boot/f3dba231-4a55-0a94-dfab-5cab1419d132@gmail.com/ > > Replacement command used: > find . -type f -exec sed -i 's/*)devfdt_get_addr_size_index(/ > *)devfdt_get_addr_size_index_ptr(/g' {} + > --- > drivers/pci/pcie_dw_mvebu.c | 6 +++--- > drivers/spi/cadence_qspi.c | 3 +-- > 2 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c > index a0b82c78..3b2ada54 100644 > --- a/drivers/pci/pcie_dw_mvebu.c > +++ b/drivers/pci/pcie_dw_mvebu.c > @@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) > return -EINVAL; > > /* Get the config space base address and size */ > - pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, > - &pcie->cfg_size); > - if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) > + pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, > + &pcie->cfg_size); > + if (!pcie->cfg_base) > return -EINVAL; > > return 0; > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index ab0a681c..93e57a54 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -378,8 +378,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) > ofnode subnode; > > plat->regbase = (void *)devfdt_get_addr_index(bus, 0); > - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, > - &plat->ahbsize); > + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); hope that ahbbase then is checked if is NULL > plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); > plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); > plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com> > -- > 2.20.1 >
Hi Johan, On Sat, Feb 25, 2023 at 8:19 PM Johan Jonker <jbx6244@gmail.com> wrote: > > The fdt_addr_t and phys_addr_t size have been decoupled. > A 32bit CPU can expect 64-bit data from the device tree parser, > so use devfdt_get_addr_size_index_ptr instead of > the devfdt_get_addr_size_index function in the various files > in the drivers directory that cast to a pointer. > > Signed-off-by: Johan Jonker <jbx6244@gmail.com> > --- > > Note: > > This is needed for a Rockchip patch serie to pass the test and > must be merged before by Rockchip maintainers: > > [PATCH v4 00/11] Fixes for Rockchip NFC driver part 1 > https://lore.kernel.org/u-boot/f3dba231-4a55-0a94-dfab-5cab1419d132@gmail.com/ > > Replacement command used: > find . -type f -exec sed -i 's/*)devfdt_get_addr_size_index(/ > *)devfdt_get_addr_size_index_ptr(/g' {} + > --- > drivers/pci/pcie_dw_mvebu.c | 6 +++--- > drivers/spi/cadence_qspi.c | 3 +-- > 2 files changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c > index a0b82c78..3b2ada54 100644 > --- a/drivers/pci/pcie_dw_mvebu.c > +++ b/drivers/pci/pcie_dw_mvebu.c > @@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) > return -EINVAL; > > /* Get the config space base address and size */ > - pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, > - &pcie->cfg_size); > - if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) > + pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, > + &pcie->cfg_size); > + if (!pcie->cfg_base) > return -EINVAL; > > return 0; > diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c > index ab0a681c..93e57a54 100644 > --- a/drivers/spi/cadence_qspi.c > +++ b/drivers/spi/cadence_qspi.c > @@ -378,8 +378,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) > ofnode subnode; > > plat->regbase = (void *)devfdt_get_addr_index(bus, 0); > - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, > - &plat->ahbsize); > + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); Please rebase the series on master (I have fixed a conflict) and test with buildman. The CI pipeline outputs this error: Building current source for 1 boards (1 thread, 64 jobs per thread) 52 aarch64: + xilinx_versal_virt 53+drivers/spi/cadence_qspi.c: In function 'cadence_spi_of_to_plat': 54+drivers/spi/cadence_qspi.c:387:25: error: implicit declaration of function 'devfdt_get_addr_size_index_ptr'; did you mean 'devfdt_get_addr_size_index'? [-Werror=implicit-function-declaration] 55+ 387 | plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); 56+ | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 57+ | devfdt_get_addr_size_index 58+drivers/spi/cadence_qspi.c:387:23: error: assignment to 'void *' from 'int' makes pointer from integer without a cast [-Werror=int-conversion] Thanks and regards, Dario > plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); > plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); > plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4); > -- > 2.20.1 >
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index a0b82c78..3b2ada54 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -569,9 +569,9 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = (void *)devfdt_get_addr_size_index(dev, 1, - &pcie->cfg_size); - if ((fdt_addr_t)pcie->cfg_base == FDT_ADDR_T_NONE) + pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, + &pcie->cfg_size); + if (!pcie->cfg_base) return -EINVAL; return 0; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index ab0a681c..93e57a54 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -378,8 +378,7 @@ static int cadence_spi_of_to_plat(struct udevice *bus) ofnode subnode; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); - plat->ahbbase = (void *)devfdt_get_addr_size_index(bus, 1, - &plat->ahbsize); + plat->ahbbase = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahbsize); plat->is_decoded_cs = dev_read_bool(bus, "cdns,is-decoded-cs"); plat->fifo_depth = dev_read_u32_default(bus, "cdns,fifo-depth", 128); plat->fifo_width = dev_read_u32_default(bus, "cdns,fifo-width", 4);
The fdt_addr_t and phys_addr_t size have been decoupled. A 32bit CPU can expect 64-bit data from the device tree parser, so use devfdt_get_addr_size_index_ptr instead of the devfdt_get_addr_size_index function in the various files in the drivers directory that cast to a pointer. Signed-off-by: Johan Jonker <jbx6244@gmail.com> --- Note: This is needed for a Rockchip patch serie to pass the test and must be merged before by Rockchip maintainers: [PATCH v4 00/11] Fixes for Rockchip NFC driver part 1 https://lore.kernel.org/u-boot/f3dba231-4a55-0a94-dfab-5cab1419d132@gmail.com/ Replacement command used: find . -type f -exec sed -i 's/*)devfdt_get_addr_size_index(/ *)devfdt_get_addr_size_index_ptr(/g' {} + --- drivers/pci/pcie_dw_mvebu.c | 6 +++--- drivers/spi/cadence_qspi.c | 3 +-- 2 files changed, 4 insertions(+), 5 deletions(-) -- 2.20.1