From patchwork Mon Sep 30 11:26:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 279117 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3B59B2C00C1 for ; Mon, 30 Sep 2013 21:27:28 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 236744A0F6; Mon, 30 Sep 2013 13:27:18 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id k-lboVa19UtX; Mon, 30 Sep 2013 13:27:17 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 431E34A0F8; Mon, 30 Sep 2013 13:27:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 410174A0E9 for ; Mon, 30 Sep 2013 13:27:03 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fZ1cJUHSfvzL for ; Mon, 30 Sep 2013 13:26:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by theia.denx.de (Postfix) with ESMTPS id 56B134A0EB for ; Mon, 30 Sep 2013 13:26:56 +0200 (CEST) Received: from sumo-PORTEGE-R700.toradex.int (46-140-72-82.static.cablecom.ch [46.140.72.82]) by mrelay.perfora.net (node=mrus2) with ESMTP (Nemesis) id 0MRXiy-1VFYyr3gvA-00SjLA; Mon, 30 Sep 2013 07:26:49 -0400 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Mon, 30 Sep 2013 13:26:06 +0200 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: X-Provags-ID: V02:K0:VijqI1NLj95OP63sv7Avsa99yFw1klsMym3J4gx7AJ2 727GXF6T9eVG6B/cxNgfQl9U/fg2abpJNUx9unRVVqQ3NKMmqM GdB7XBSn+Zywb3xYxA97tcKysCt2vo0DmFrrtnHKIUyZJZVm3D ZO1yz004KGlL/6z2nl5fcoOHOYReSyB90rfxWX+2JAZvTPtzID AxsXHmbCS9BJ+gcESzCdmmoueHzolbO9rujHnBmJYKQ8D+Wh4H 4vJ3WFAO40Mid0GnNU3WfuoitupasBCbeQK/LklhYsncSUV+UQ KjSINk8xZsAJTmYR8f4eR/QbzmwWtIHOpCNUeLEktvlkFmfFPk jvp8q772v+p5LI6/x5WXObxgfFMsmz+IKywWoc3F+NCi8m8ASd j1fDLKKrBqbkHtzszh04j+rapnl/sPlwI+AKGxl+6Wb1R7X6U5 EshoHFT1+rsW/lzD6n98N+dkvYw== Cc: Marcel Ziswiler Subject: [U-Boot] [PATCH v2 01/10] arm: vf610: fix anadig register struct X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The anadig_reg structure started at the wrong offset (fixed by adding resvA[4]), was missing some reserved field required for alignment purpose (resvB[3] between pll4_denom and pll6_ctrl) and further contained too short a reserved field causing further miss-alignment (resv10[7]). Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler --- arch/arm/include/asm/arch-vf610/crm_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda..57a0242 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,6 +55,7 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 resvA[4]; u32 pll3_ctrl; u32 resv0[3]; u32 pll7_ctrl; @@ -72,12 +73,13 @@ struct anadig_reg { u32 pll4_num; u32 resv7[3]; u32 pll4_denom; + u32 resvB[3]; u32 pll6_ctrl; u32 resv8[3]; u32 pll6_num; u32 resv9[3]; u32 pll6_denom; - u32 resv10[3]; + u32 resv10[7]; u32 pll5_ctrl; u32 resv11[3]; u32 pll3_pfd;