diff mbox series

mips: dts: Fix device tree warnings for PIC32MZDA

Message ID VI1P190MB01416EBB507E2D0BA9F67461FB2E0@VI1P190MB0141.EURP190.PROD.OUTLOOK.COM
State Accepted
Commit 0723c2ddeb8a5446a4b32e7583461efe50d0fe6c
Delegated to: Daniel Schwierzeck
Headers show
Series mips: dts: Fix device tree warnings for PIC32MZDA | expand

Commit Message

John Robertson Sept. 1, 2020, 4:14 a.m. UTC 
Signed-off-by: John Robertson <john.robertson@simiatec.com>
---

 arch/mips/dts/pic32mzda.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

Comments

Daniel Schwierzeck Sept. 19, 2020, 7:31 p.m. UTC | #1 
Am Dienstag, den 01.09.2020, 04:14 +0000 schrieb John Robertson:
> Signed-off-by: John Robertson <john.robertson@simiatec.com>
> ---
> 
>  arch/mips/dts/pic32mzda.dtsi | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

applied to u-boot-mips/fixes, thanks.
diff mbox series

Patch

diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
index 4c8b7a9a0b..8aff9eb812 100644
--- a/arch/mips/dts/pic32mzda.dtsi
+++ b/arch/mips/dts/pic32mzda.dtsi
@@ -26,8 +26,13 @@ 
 	};
 
 	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
 		cpu@0 {
 			compatible = "mips,mips14kc";
+			device-type = "cpu";
+			reg = <0>;
 		};
 	};
 
@@ -40,6 +45,7 @@ 
 	uart1: serial@1f822000 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822000 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
 		status = "disabled";
 		clocks = <&clock PB2CLK>;
@@ -48,6 +54,7 @@ 
 	uart2: serial@1f822200 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822200 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB2CLK>;
 		status = "disabled";
@@ -56,6 +63,7 @@ 
 	uart6: serial@1f822a00 {
 		compatible = "microchip,pic32mzda-uart";
 		reg = <0x1f822a00 0x50>;
+		interrupt-parent = <&evic>;
 		interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB2CLK>;
 		status = "disabled";
@@ -153,6 +161,7 @@ 
 	sdhci: sdhci@1f8ec000 {
 		compatible = "microchip,pic32mzda-sdhci";
 		reg = <0x1f8ec000 0x100>;
+		interrupt-parent = <&evic>;
 		interrupts = <191 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock REF4CLK>, <&clock PB5CLK>;
 		clock-names = "base_clk", "sys_clk";
@@ -164,6 +173,7 @@ 
 	ethernet: ethernet@1f882000 {
 		compatible = "microchip,pic32mzda-eth";
 		reg = <0x1f882000 0x1000>;
+		interrupt-parent = <&evic>;
 		interrupts = <153 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB5CLK>;
 		status = "disabled";
@@ -176,6 +186,7 @@ 
 		reg = <0x1f8e3000 0x1000>,
 		      <0x1f884000 0x1000>;
 		reg-names = "mc", "control";
+		interrupt-parent = <&evic>;
 		interrupts = <132 IRQ_TYPE_EDGE_RISING>,
 			     <133 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&clock PB5CLK>;