From patchwork Mon May 14 20:58:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 913230 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=de.pepperl-fuchs.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40lCjZ6Wh2z9s0q for ; Tue, 15 May 2018 06:58:58 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 36D99C21F87; Mon, 14 May 2018 20:58:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 44D5CC21F87; Mon, 14 May 2018 20:58:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 78FB4C21F87; Mon, 14 May 2018 20:58:49 +0000 (UTC) Received: from mailout.pepperl-fuchs.com (mailout.pepperl-fuchs.com [212.21.166.229]) by lists.denx.de (Postfix) with ESMTPS id 25A6EC21C6A for ; Mon, 14 May 2018 20:58:49 +0000 (UTC) Received: from PFDE-CAS1.EU.P-F.BIZ (pfde-cas1.eu.p-f.biz [172.24.5.133]) by mailout.pepperl-fuchs.com (Postfix) with ESMTP id E20CE81A04; Mon, 14 May 2018 22:58:48 +0200 (CEST) Received: from PFDE-MX11.EU.P-F.BIZ ([fe80::d571:1e54:8f01:3111]) by PFDE-CAS1.EU.P-F.BIZ ([::1]) with mapi id 14.03.0301.000; Mon, 14 May 2018 22:58:48 +0200 From: Goldschmidt Simon To: Marek Vasut Thread-Topic: [PATCH] arm: socfpga: correctly reserve SRAM for boot counter Thread-Index: AdPrxhE6ENuSeZUxQXGccNU/FRnE8Q== Date: Mon, 14 May 2018 20:58:47 +0000 Message-ID: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.24.5.147] x-exclaimer-md-config: 1e262833-c6b8-4d86-a546-40bddc43f2e2 MIME-Version: 1.0 Cc: "u-boot@lists.denx.de" , Stefan Roese Subject: [U-Boot] [PATCH] arm: socfpga: correctly reserve SRAM for boot counter X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Bootcounter for is1 and sr1500 boards somewhat relied on struct global data alignment gap at the end of internal SRAM. Let's fix this by explicitly reserving some bytes. Signed-off-by: Simon Goldschmidt --- include/configs/socfpga_common.h | 6 +++++- include/configs/socfpga_is1.h | 3 ++- include/configs/socfpga_sr1500.h | 3 ++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 4de2aa7929..1934aea86d 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -35,8 +35,12 @@ #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */ #endif +/* Reserve bytes at the end of SRAM? */ +#ifndef SOCFPGA_INIT_RAM_END_RESERVE +#define SOCFPGA_INIT_RAM_END_RESERVE 0 +#endif #define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + (CONFIG_SYS_INIT_RAM_SIZE - SOCFPGA_INIT_RAM_END_RESERVE) #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h index c233c208a5..b243fd29cd 100644 --- a/include/configs/socfpga_is1.h +++ b/include/configs/socfpga_is1.h @@ -27,8 +27,9 @@ #include /* - * Bootcounter + * Bootcounter (preserve the last 2 lwords for the boot-counter) */ +#define CONFIG_SYS_INIT_RAM_END_RESERVE 8 #define CONFIG_SYS_BOOTCOUNT_BE #endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h index c835d23235..ff71712566 100644 --- a/include/configs/socfpga_sr1500.h +++ b/include/configs/socfpga_sr1500.h @@ -26,8 +26,9 @@ #define CONFIG_SPI_N25Q256A_RESET /* - * Bootcounter + * Bootcounter (preserve the last 2 lwords for the boot-counter) */ +#define SOCFPGA_INIT_RAM_END_RESERVE 8 #define CONFIG_SYS_BOOTCOUNT_BE /* Environment setting for SPI flash */