@@ -20,6 +20,13 @@ static void *base = (void *)IOMUXC_BASE_ADDR;
*/
void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
{
+#if defined CONFIG_MX6SL
+ bool lve = false;
+
+ if(pad & PAD_CTL_LVE)
+ lve = true;
+#endif
+
u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
u32 sel_input_ofs =
@@ -30,6 +37,12 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
(pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
+#if defined CONFIG_MX6SL
+ /* Check whether LVE bit needs to be set */
+ if (lve)
+ pad_ctrl |= PAD_CTL_LVE_BIT;
+#endif
+
if (mux_ctrl_ofs)
__raw_writel(mux_mode, base + mux_ctrl_ofs);
b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -42,7 +42,7 @@
* MUX_MODE + SION: 36..40 (5)
* PAD_CTRL + NO_PAD_CTRL: 41..58 (18)
* SEL_INP: 59..62 (4)
- * reserved: 63 (1)
+ * LVE: 63 (1)
*/
typedef u64 iomux_v3_cfg_t;
@@ -88,6 +88,8 @@ typedef u64 iomux_v3_cfg_t;
#ifdef CONFIG_MX6
#define PAD_CTL_HYS (1 << 16)
+#define PAD_CTL_LVE 0x8000000000000000
+#define PAD_CTL_LVE_BIT (1 << 22)
#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE)
#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE)