diff mbox

[U-Boot] mx28: booting u-boot via USB

Message ID CAOMZO5AMnLLqW+ZpNTzZrvHp476d3gtCSXPSLUkyo39bFD5HcQ@mail.gmail.com
State Superseded
Headers show

Commit Message

Fabio Estevam Jan. 31, 2012, 2:53 p.m. UTC 
On 1/31/12, Matthias Fuchs <matthias.fuchs@esd.eu> wrote:

> The USB boot mechanism is not documented that detailed.
> Is it possible that the SPL code overwrites the bootroms ivt and
> in consequence crashes the bootrom's USB code? Any further ideas?

Completely untested, but please give it a try:

Comments

Matthias Fuchs Jan. 31, 2012, 3:34 p.m. UTC | #1 
Hi Fabio,

On 31.01.2012 15:53, Fabio Estevam wrote:
> On 1/31/12, Matthias Fuchs <matthias.fuchs@esd.eu> wrote:
> 
>> The USB boot mechanism is not documented that detailed.
>> Is it possible that the SPL code overwrites the bootroms ivt and
>> in consequence crashes the bootrom's USB code? Any further ideas?
> 
> Completely untested, but please give it a try:
Good idea. But it does not help. I expect, that the bootrom enables
all required clocks. As long as the SPL does not turn them of they
should stay enabled because of the set/clear-register pairs.

Matthias

> 
> diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> index 00493b8..313b5c7 100644
> --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> +++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
> @@ -201,8 +201,8 @@ void mx28_mem_init(void)
>         writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
>                 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
> 
> -       /* Power up PLL0 */
> -       writel(CLKCTRL_PLL0CTRL0_POWER,
> +       /* Power up PLL0 and USB clocks */
> +       writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
>                 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
> 
>         early_delay(11000);
> diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> index 380b120..e55f552 100644
> --- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> +++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
> @@ -45,7 +45,7 @@ void mx28_power_clock2pll(void)
>         struct mx28_clkctrl_regs *clkctrl_regs =
>                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
> 
> -       writel(CLKCTRL_PLL0CTRL0_POWER,
> +       writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
>                 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
>         early_delay(100);
>         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
>
diff mbox

Patch

diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
index 00493b8..313b5c7 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -201,8 +201,8 @@  void mx28_mem_init(void)
        writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
                &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);

-       /* Power up PLL0 */
-       writel(CLKCTRL_PLL0CTRL0_POWER,
+       /* Power up PLL0 and USB clocks */
+       writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
                &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);

        early_delay(11000);
diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
index 380b120..e55f552 100644
--- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
@@ -45,7 +45,7 @@  void mx28_power_clock2pll(void)
        struct mx28_clkctrl_regs *clkctrl_regs =
                (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;

-       writel(CLKCTRL_PLL0CTRL0_POWER,
+       writel(CLKCTRL_PLL0CTRL0_EN_USB_CLKS | CLKCTRL_PLL0CTRL0_POWER,
                &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
        early_delay(100);
        writel(CLKCTRL_CLKSEQ_BYPASS_CPU,