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[U-Boot] Please pull u-boot-riscv

Message ID CAN5B=e+QmndHcc9Uxqr5tHeeBhC9s0fqG9NYxooyqr_VCxZ01g@mail.gmail.com
State Accepted
Delegated to: Tom Rini
Headers show
Series [U-Boot] Please pull u-boot-riscv | expand

Pull-request

git://git.denx.de/u-boot-riscv.git

Message

Rick Chen Dec. 5, 2018, 7:12 a.m. UTC 
Hi Tom,

Please pull some riscv update:
1. Fix BBL may be corrupted problem.
2. Support U-Boot run in S-mode.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/463646974

Thanks

Rick


The following changes since commit 2e2a2a5d4f0c2e2642326d9000ce1f1553632e6a:

  Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-12-04
19:22:31 -0500)

are available in the Git repository at:

  git://git.denx.de/u-boot-riscv.git

for you to fetch changes up to 48cbf6246052de10d35b616b5efb2f783904a49d:

  riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
(2018-12-05 14:14:16 +0800)

----------------------------------------------------------------
Anup Patel (3):
      riscv: Add kconfig option to run U-Boot in S-mode
      riscv: qemu: Use different SYS_TEXT_BASE for S-mode
      riscv: Add S-mode defconfigs for QEMU virt machine

Rick Chen (1):
      riscv: ax25-ae350: Pass dtb address to u-boot with a1 register

 arch/riscv/Kconfig                      |  5 +++++
 arch/riscv/cpu/start.S                  | 25 +++++++++++++++----------
 arch/riscv/include/asm/encoding.h       |  6 ++++++
 arch/riscv/lib/interrupts.c             | 31 ++++++++++++++++++++++---------
 board/AndesTech/ax25-ae350/ax25-ae350.c |  3 ++-
 board/emulation/qemu-riscv/Kconfig      |  3 ++-
 board/emulation/qemu-riscv/MAINTAINERS  |  2 ++
 configs/qemu-riscv32_smode_defconfig    | 10 ++++++++++
 configs/qemu-riscv64_smode_defconfig    | 11 +++++++++++
 9 files changed, 75 insertions(+), 21 deletions(-)
 create mode 100644 configs/qemu-riscv32_smode_defconfig
 create mode 100644 configs/qemu-riscv64_smode_defconfig

Comments

Tom Rini Dec. 6, 2018, 1:31 a.m. UTC | #1 
On Wed, Dec 05, 2018 at 03:12:29PM +0800, Rick Chen wrote:

> Hi Tom,
> 
> Please pull some riscv update:
> 1. Fix BBL may be corrupted problem.
> 2. Support U-Boot run in S-mode.
> 
> https://travis-ci.org/rickchen36/u-boot-riscv/builds/463646974
> 
> Thanks
> 
> Rick
> 
> 
> The following changes since commit 2e2a2a5d4f0c2e2642326d9000ce1f1553632e6a:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-sh (2018-12-04
> 19:22:31 -0500)
> 
> are available in the Git repository at:
> 
>   git://git.denx.de/u-boot-riscv.git
> 
> for you to fetch changes up to 48cbf6246052de10d35b616b5efb2f783904a49d:
> 
>   riscv: ax25-ae350: Pass dtb address to u-boot with a1 register
> (2018-12-05 14:14:16 +0800)
> 

Applied to u-boot/master, thanks!