From patchwork Thu Jul 19 07:13:32 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Javier Martinez Canillas X-Patchwork-Id: 171895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id C4A232C011F for ; Thu, 19 Jul 2012 17:13:43 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 54898280A5; Thu, 19 Jul 2012 09:13:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id vB-n3lsWutwx; Thu, 19 Jul 2012 09:13:42 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B8B7628097; Thu, 19 Jul 2012 09:13:39 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7883A28097 for ; Thu, 19 Jul 2012 09:13:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gaevaFJFXD0D for ; Thu, 19 Jul 2012 09:13:36 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-ob0-f172.google.com (mail-ob0-f172.google.com [209.85.214.172]) by theia.denx.de (Postfix) with ESMTPS id 5732828095 for ; Thu, 19 Jul 2012 09:13:34 +0200 (CEST) Received: by obbwc20 with SMTP id wc20so3238612obb.3 for ; Thu, 19 Jul 2012 00:13:33 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:x-originating-ip:in-reply-to:references:date :message-id:subject:from:to:cc:content-type :content-transfer-encoding:x-gm-message-state; bh=vmScsO/JflnNENdYBfNMHJoKf2A9ftkWX8+uBrfwJTU=; b=GLm4N2O/KjLayfuKhjm9t6VgosPglcIdDlqBZhUa/vzmoIgDib/lWVb4rSukT5GuyK 6kjNalSFjLIjr4iMP5IDZeUnCOstVjYVRuVNtZ7XZ/i3x0PmMzSH5PU4cu2GCqSDv8Qk 0qr7/s4lF5DtZMyWuLr1xrgvs/fkviB8omR6Ou8eIwxrfoBzlf43O4v7wev68hKJYRKc ZNW0uCeqtQ1D6kWwBmdyVsZm8JuIJMfuj5wJIslTE5cK+a6MVQf6GUmaKW4Qn5Fi6P1H 0YfWktVAa4r2v8btno5mBp5vG+3itY6ycadRub4nJqxGnaGJd+Wn0FLoVBgcDvVOw2XY Q4Ag== MIME-Version: 1.0 Received: by 10.182.145.8 with SMTP id sq8mr922456obb.50.1342682012736; Thu, 19 Jul 2012 00:13:32 -0700 (PDT) Received: by 10.60.36.233 with HTTP; Thu, 19 Jul 2012 00:13:32 -0700 (PDT) X-Originating-IP: [95.23.150.222] In-Reply-To: References: <1342484117-4740-1-git-send-email-javier@dowhile0.org> <20120718174904.1d9842a7@skate> Date: Thu, 19 Jul 2012 09:13:32 +0200 Message-ID: From: Javier Martinez Canillas To: =?UTF-8?Q?Enric_Balletb=C3=B2_i_Serra?= X-Gm-Message-State: ALoCoQme11prklLNpQckRMxDLj6CaMAJ7OH3j09vAB+HPgxkNejrsB6qNTkYBQNvmorTl2i19TuF Cc: Thomas Petazzoni , u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH u-boot-arm/next v2 1/1] OMAP3: igep00x0: add SPL support for IGEP-based boards X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de On Thu, Jul 19, 2012 at 8:56 AM, Enric Balletbò i Serra wrote: > 2012/7/19 Javier Martinez Canillas : >> On Wed, Jul 18, 2012 at 5:49 PM, Thomas Petazzoni >> wrote: >>> Le Tue, 17 Jul 2012 02:15:17 +0200, >>> Javier Martinez Canillas a écrit : >>> >>>> +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, >>>> + u32 *mr) >>>> +{ >>>> + *mr = MICRON_V_MR_165; >>>> +#ifdef CONFIG_BOOT_NAND >>>> + *mcfg = MICRON_V_MCFG_165(512 << 20); >>>> + *ctrla = MICRON_V_ACTIMA_165; >>>> + *ctrlb = MICRON_V_ACTIMB_165; >>>> + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; >>> >>> I thought the NAND version of the IGEPv2 was capable of using the 200 >>> Mhz timings. At least, from the limited testing I had done, it seemed >>> to work. >>> >>> Best regards, >>> >>> Thomas >>> -- >> >> Hi Thomas, >> >> Yes, you are right. I just tested the following patch on my NAND >> version IGEPv2 and it seems to work just fine. >> >> Do you know if the OneNAND version also supports 200 MHz timings? If I >> remember correctly the OMAP3730 version did but the OMAP3530 didn't. >> >> I guess Enric knows the answer :-) >> > > Both memories can work at 200MHz, I guess the limitation is on the > processor that is populated on the board. If the IGEP board comes with > OMAP3530 should work at 166MHz, if comes with DM3730 can work at > 200MHz. > > Cheers, > Enric Hi Enric, That's what I remembered but I wasn't sure about it, thanks for the clarification. What do you think about this patch then? #endif diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c index 40436d6..a4d099a 100644 --- a/board/isee/igep0020/igep0020.c +++ b/board/isee/igep0020/igep0020.c @@ -77,15 +77,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } #endif } #endif diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c index 41a7548..4f8b645 100644 --- a/board/isee/igep0030/igep0030.c +++ b/board/isee/igep0030/igep0030.c @@ -64,15 +64,23 @@ void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, { *mr = MICRON_V_MR_165; #ifdef CONFIG_BOOT_NAND - *mcfg = MICRON_V_MCFG_165(512 << 20); - *ctrla = MICRON_V_ACTIMA_165; - *ctrlb = MICRON_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mcfg = MICRON_V_MCFG_200(512 << 20); + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; #else - *mcfg = NUMONYX_V_MCFG_165(512 << 20); - *ctrla = NUMONYX_V_ACTIMA_165; - *ctrlb = NUMONYX_V_ACTIMB_165; - *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (get_cpu_family() == CPU_OMAP34XX) { + *mcfg = NUMONYX_V_MCFG_165(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + } else { + *mcfg = NUMONYX_V_MCFG_200(512 << 20); + *ctrla = NUMONYX_V_ACTIMA_200; + *ctrlb = NUMONYX_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } #endif }