From patchwork Mon May 25 14:35:05 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 476219 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 030661401B5 for ; Tue, 26 May 2015 00:35:45 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=WtB0fAov; dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9E9F74B6A9; Mon, 25 May 2015 16:35:37 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id RKT16RBL3C3I; Mon, 25 May 2015 16:35:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2936A4B6BE; Mon, 25 May 2015 16:35:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 903284B691 for ; Mon, 25 May 2015 16:35:29 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id A_9ezI9y_cW1 for ; Mon, 25 May 2015 16:35:29 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qg0-f54.google.com (mail-qg0-f54.google.com [209.85.192.54]) by theia.denx.de (Postfix) with ESMTPS id 2BC6F4B68A for ; Mon, 25 May 2015 16:35:25 +0200 (CEST) Received: by qgez61 with SMTP id z61so45996620qge.1 for ; Mon, 25 May 2015 07:35:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:from:to:subject:date:in-reply-to:references:mime-version :content-type; bh=t5mWNCH6UmUuypfsX4RRK4VY/nitS/qsZmve5CvffgY=; b=WtB0fAovlg2l/IjPWJfMcIuP5i7Id2PBSfuitBOmsfhnOvyVsaWK48Us50wF5uzOFV 9PKqxUKDE8577YLvd7I8Nj38fiXEHtIZMSEM10ReAOaU983FIuOqehgG/CPNmkSB89H8 zgNcjqsiSmFWte4iqyZJAooWDRIyU1rQa1qvimMhNh3CAUFg4g6RBwQNKMgTRzGUqSnS dN5le0DSXmYTUQ+4jGBfOpmAg6+L8+27JSSX/hg8Wv5Hxbauz/2vqlyHkOBTirvCqQWq lLmPYR04/HB5Ev5ld04QDVRWqSIqOIUYBhn9MSzTSUsXQcrF3LHx2WV2xTHmCk48G9YX 4LUA== X-Received: by 10.140.87.97 with SMTP id q88mr27103001qgd.99.1432564524807; Mon, 25 May 2015 07:35:24 -0700 (PDT) Received: from mail.hotmail.com (blu004-wss1s6.hotmail.com. [134.170.2.221]) by mx.google.com with ESMTPSA id z13sm5763959qkg.44.2015.05.25.07.35.24 (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 25 May 2015 07:35:24 -0700 (PDT) Received: from BLU437-SMTP81 ([134.170.2.215]) by BLU004-WSS1S6.hotmail.com over TLS secured channel with Microsoft SMTPSVC(7.5.7601.22751); Mon, 25 May 2015 07:35:23 -0700 X-TMN: [5E4DQ5FJNTrqVYRuMAC5ZbgB8oyTjs2r] Message-ID: From: Bin Meng To: Simon Glass , U-Boot Mailing List Date: Mon, 25 May 2015 22:35:05 +0800 X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1432564507-23841-1-git-send-email-bmeng.cn@gmail.com> References: <1432564507-23841-1-git-send-email-bmeng.cn@gmail.com> X-OriginalArrivalTime: 25 May 2015 14:35:23.0193 (UTC) FILETIME=[0878BA90:01D096F8] MIME-Version: 1.0 Subject: [U-Boot] [PATCH v2 2/4] x86: Document irq router device tree bindings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Describe all required properties needed by the irq router device tree. Signed-off-by: Bin Meng Acked-by: Simon Glass --- Changes in v2: - Fix typo of 'configuration' doc/device-tree-bindings/misc/intel,irq-router.txt | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 doc/device-tree-bindings/misc/intel,irq-router.txt diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt new file mode 100644 index 0000000..598b4b1 --- /dev/null +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -0,0 +1,50 @@ +Intel Interrupt Router Device Binding +===================================== + +The device tree node which describes the operation of the Intel Interrupt Router +device is as follows: + +Required properties : +- reg : Specifies the interrupt router's PCI configuration space address as + defined by the Open Firmware spec. +- compatible = "intel,irq-router" +- intel,pirq-config : Specifies the IRQ routing register programming mechanism. + Valid values are: + "pci": IRQ routing is controlled by PCI configuration registers + "ibase": IRQ routing is in the memory-mapped IBASE register block +- intel,ibase-offset : IBASE register offset in the interrupt router's PCI + configuration space, required only if intel,pirq-config = "ibase". +- intel,pirq-link : Specifies the PIRQ link information with two cells. The + first cell is the register offset that controls the first PIRQ link routing. + The second cell is the total number of PIRQ links the router supports. +- intel,pirq-mask : Specifies the IRQ mask reprenting the 16 IRQs in 8259 PIC. + Bit N is 1 means IRQ N is available to be routed. +- intel,pirq-routing : Specifies all PCI devices' IRQ routing information, + encoded as 3 cells a group for a device. The first cell is the device's PCI + bus number, device number and function number encoding with PCI_BDF() macro. + The second cell is the PCI interrupt pin used by this device. The last cell + is which PIRQ line the PCI interrupt pin is routed to. + + +Example +------- + +#include + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "pci"; + intel,pirq-link = <0x60 8>; + intel,pirq-mask = <0xdef8>; + intel,pirq-routing = < + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQB + PCI_BDF(0, 8, 0) INTA PIRQC + PCI_BDF(0, 8, 1) INTB PIRQD + PCI_BDF(1, 6, 0) INTA PIRQE + PCI_BDF(1, 6, 1) INTB PIRQF + PCI_BDF(1, 6, 2) INTC PIRQG + PCI_BDF(1, 6, 3) INTD PIRQH + >; + };