From patchwork Thu Nov 12 08:35:43 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1398756 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=85.214.62.61; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=kvL66K0U; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4CWw2K5vrNz9s0b for ; Thu, 12 Nov 2020 19:37:13 +1100 (AEDT) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 148F882515; Thu, 12 Nov 2020 09:36:28 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.b="kvL66K0U"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 9FF6482571; Thu, 12 Nov 2020 09:35:58 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=0.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,MIME_BASE64_TEXT,RDNS_NONE,SPF_HELO_NONE, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw02.mediatek.com (unknown [1.203.163.81]) by phobos.denx.de (Postfix) with ESMTP id 5015A82515 for ; Thu, 12 Nov 2020 09:35:50 +0100 (CET) Authentication-Results: phobos.denx.de; dmarc=pass (p=none dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: 29046875f0a64f2ab5423278b476950d-20201112 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=WkmGfgNLCNIAeZmRjlSQCY0dqE9xz12R9d5GYpi6Z0I=; b=kvL66K0U4ZEAwDkxkPaw6mNi5GklYsQSDJmKZrutAEI7TLQUKMdOCaasO9gJLib4wJcuEvbvBxZ/6qD6lQvxpPfanNbdvaGwnbf1cQ4ZxrHwyyhJX9+Ty/DhTpT2Zh02WxwZAZcGRN1gFtO5rcehb3P/cP4fmr63SEDrUgfioTQ=; X-UUID: 29046875f0a64f2ab5423278b476950d-20201112 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 562866496; Thu, 12 Nov 2020 16:35:46 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Nov 2020 16:35:45 +0800 Received: from mcddlt001.mediatek.inc (10.19.240.15) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Nov 2020 16:35:44 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Daniel Schwierzeck , Stefan Roese , Stefan Roese , Weijie Gao Subject: [PATCH v4 06/23] mips: mtmips: add support to initialize SDRAM Date: Thu, 12 Nov 2020 16:35:43 +0800 Message-ID: <917816d5b165f597412b1f0a6b46de92f04e5e6a.1605169080.git.weijie.gao@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: MIME-Version: 1.0 X-TM-SNTS-SMTP: 284CB0149A2EE3F4B32BEE2CD8A92756AE3ADA808A6AB56093611945A3771D572000:8 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean This patch adds support for mtmips SoCs to initialize the SDRAM. Reviewed-by: Stefan Roese Signed-off-by: Weijie Gao --- v4 changes: none v3 changes: none v2 changes: none --- arch/mips/mach-mtmips/ddr_init.c | 59 ++++++++++++++++++++++++ arch/mips/mach-mtmips/include/mach/ddr.h | 4 ++ 2 files changed, 63 insertions(+) diff --git a/arch/mips/mach-mtmips/ddr_init.c b/arch/mips/mach-mtmips/ddr_init.c index 6c6d0933f2..9c986daea6 100644 --- a/arch/mips/mach-mtmips/ddr_init.c +++ b/arch/mips/mach-mtmips/ddr_init.c @@ -15,6 +15,13 @@ #define DDR_BW_TEST_PAT 0xaa5555aa +static const u32 sdr_size_cfg1[] = { + [DRAM_8MB] = (1 << NUMROWS_S), + [DRAM_16MB] = (1 << NUMROWS_S) | (1 << NUMCOLS_S), + [DRAM_32MB] = (2 << NUMROWS_S) | (1 << NUMCOLS_S), + [DRAM_64MB] = (2 << NUMROWS_S) | (2 << NUMCOLS_S), +}; + static const u32 dram_size[] = { [DRAM_8MB] = SZ_8M, [DRAM_16MB] = SZ_16M, @@ -193,3 +200,55 @@ void ddr2_init(struct mc_ddr_init_param *param) param->memsize = dram_size[sz]; param->bus_width = bw; } + +static void mc_sdr_init(void __iomem *memc, mc_reset_t mc_reset, u32 cfg0, + u32 cfg1) +{ + mc_reset(1); + __udelay(200); + mc_reset(0); + + writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG); + writel(cfg1, memc + MEMCTL_SDRAM_CFG1_REG); + + while (!(readl(memc + MEMCTL_SDRAM_CFG1_REG) & SDRAM_INIT_DONE)) + ; + + clrsetbits_32(memc + MEMCTL_PWR_SAVE_CNT_REG, SR_TAR_CNT_M, + 1 << SR_TAR_CNT_S); + + setbits_32(memc + MEMCTL_DDR_SELF_REFRESH_REG, SR_AUTO_EN); +} + +void sdr_init(struct mc_ddr_init_param *param) +{ + enum mc_dram_size sz; + u32 cfg1; + + cfg1 = param->sdr_cfg1 | SDRAM_INIT_START; + cfg1 &= ~(NUMCOLS_M | NUMROWS_M); + + /* First initialization, determine SDR capacity */ + mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, + cfg1 | sdr_size_cfg1[DRAM_64MB]); + + if (dram_addr_test_bit(9)) { + sz = DRAM_8MB; + } else { + if (dram_addr_test_bit(10)) { + if (dram_addr_test_bit(23)) + sz = DRAM_16MB; + else + sz = DRAM_32MB; + } else { + sz = DRAM_64MB; + } + } + + /* Final initialization */ + mc_sdr_init(param->memc, param->mc_reset, param->sdr_cfg0, + cfg1 | sdr_size_cfg1[sz]); + + /* Return actual DDR configuration */ + param->memsize = dram_size[sz]; +} diff --git a/arch/mips/mach-mtmips/include/mach/ddr.h b/arch/mips/mach-mtmips/include/mach/ddr.h index f92198137b..15ff66ace6 100644 --- a/arch/mips/mach-mtmips/include/mach/ddr.h +++ b/arch/mips/mach-mtmips/include/mach/ddr.h @@ -35,6 +35,9 @@ typedef void (*mc_reset_t)(int assert); struct mc_ddr_init_param { void __iomem *memc; + u32 sdr_cfg0; + u32 sdr_cfg1; + u32 dq_dly; u32 dqs_dly; @@ -45,6 +48,7 @@ struct mc_ddr_init_param { u32 bus_width; }; +void sdr_init(struct mc_ddr_init_param *param); void ddr1_init(struct mc_ddr_init_param *param); void ddr2_init(struct mc_ddr_init_param *param); void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);