From patchwork Wed Apr 8 13:20:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sanchayan Maity X-Patchwork-Id: 459253 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4D6931401DC for ; Wed, 8 Apr 2015 23:23:07 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=pA9t6tAD; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1E9C8A74BC; Wed, 8 Apr 2015 15:22:58 +0200 (CEST) X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3UX4qNw3EWvF; Wed, 8 Apr 2015 15:22:57 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AB07DA749E; Wed, 8 Apr 2015 15:22:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37AD3A748F for ; Wed, 8 Apr 2015 15:22:49 +0200 (CEST) X-Amavis-Alert: BAD HEADER SECTION, Duplicate header field: "References" Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3SMYBeqM6OzN for ; Wed, 8 Apr 2015 15:22:49 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-pd0-f170.google.com (mail-pd0-f170.google.com [209.85.192.170]) by theia.denx.de (Postfix) with ESMTPS id A38DCA74A5 for ; Wed, 8 Apr 2015 15:22:34 +0200 (CEST) Received: by pdbqa5 with SMTP id qa5so58285033pdb.1 for ; Wed, 08 Apr 2015 06:22:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=dger48TAlYy2x0qBW/J1tsDn6vU3jxvbrKFsHAnSNuY=; b=pA9t6tADJSn8uiLVEvMtBmV3v09i8l7NmK1q0KcBtt2k32u+XbPgBlANku/B5HQ3eY pYqZgf6Cns8eNc8aO3AaJRhz/EBqB9TcYfBw+09NU7CtnOHwMSJcXigSF74lPM3LUYGq 1AOKPP92j24itZoPPSsMy8DOFB4KhTZLMNHkVDB4melN9z9bxWpGZ/sEUwz5afy1+dpk C/z4Bqhiz+eTgydflCBKAvHOSvPU+vVuSBEbcLkfLs3ssgs3CDKYzNBNJJ6yu/8ymSH0 4XOWOPTkGvEPxZQlWkUuFI4g9QfCMZWNk0EXIUz3ZPmRa0gTVZYAjmatblkDPYARqyeQ FFWQ== X-Received: by 10.66.121.129 with SMTP id lk1mr47236084pab.155.1428499353499; Wed, 08 Apr 2015 06:22:33 -0700 (PDT) Received: from localhost ([115.115.225.206]) by mx.google.com with ESMTPSA id mx5sm11334172pdb.75.2015.04.08.06.22.31 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Apr 2015 06:22:32 -0700 (PDT) From: Sanchayan Maity To: u-boot@lists.denx.de, sbabic@denx.de Date: Wed, 8 Apr 2015 18:50:08 +0530 Message-Id: <8c0da8394309a2df54b1bc187751c38ef4205551.1428497492.git.maitysanchayan@gmail.com> X-Mailer: git-send-email 2.3.5 In-Reply-To: References: In-Reply-To: References: Cc: marex@denx.de, bhuvanchandra.dv@toradex.com, trini@konsulko.com, marcel@ziswiler.com Subject: [U-Boot] [PATCH v2 4/6] ARM: vf610: Enable caches X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Stefan Agner Enables caches which provides a rather huge speedup of the boot loader. Also mark the on-chip RAM as cachable since this is the area U-Boot runs from. Signed-off-by: Sanchayan Maity --- arch/arm/cpu/armv7/vf610/generic.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index 3bdc221..1bb9b8e 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -342,3 +342,19 @@ int get_clocks(void) #endif return 0; } + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) + enum dcache_option option = DCACHE_WRITETHROUGH; +#else + enum dcache_option option = DCACHE_WRITEBACK; +#endif + dcache_enable(); + icache_enable(); + + /* Enable caching on OCRAM */ + mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR, IRAM_SIZE, option); +} +#endif