From patchwork Tue Sep 17 10:45:06 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 275428 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 894B32C00DA for ; Tue, 17 Sep 2013 20:52:26 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9CFF94A0D0; Tue, 17 Sep 2013 12:52:14 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nd1izTtX4ZQZ; Tue, 17 Sep 2013 12:52:14 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 884B14A0EC; Tue, 17 Sep 2013 12:52:10 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6EB074A09D for ; Tue, 17 Sep 2013 12:52:02 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ejixme4vGMYV for ; Tue, 17 Sep 2013 12:51:56 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.194]) by theia.denx.de (Postfix) with ESMTPS id 1FAD54A0C9 for ; Tue, 17 Sep 2013 12:51:36 +0200 (CEST) Received: from sumo-PORTEGE-R700.toradex.int (46-140-72-82.static.cablecom.ch [46.140.72.82]) by mrelay.perfora.net (node=mrus0) with ESMTP (Nemesis) id 0MMChx-1VGefB1uDV-0086gz; Tue, 17 Sep 2013 06:46:16 -0400 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Tue, 17 Sep 2013 12:45:06 +0200 Message-Id: <86ae7d0a8914a2e3c21009b4e9eb8f3c92e343fb.1379414181.git.marcel@ziswiler.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: X-Provags-ID: V02:K0:gcHCjFazDhQOCXi2ly0Me+aXcg7IHlXZABEUyBCsKnl sahQBm4alvwRdAm91kBV/ezN6fcK6k+b5HlOkpO60sL4Env3ez 2G84qpBPUVEjp2ZKSE9/NTWso3iHmVezGdwds8LPdxU4MCi3lz fGFfL68TzcLlChPTJYqWHxBcoMlvH9Cc6lPOIqmSlkrS8povTY GVkPHDbTzH6g18noNovvAoM9EdXcCX61GYyHHi2ex7KjrNKsDE dB8h5iG99hpCAJxadoXDGetZbUG/6ZUUoiFJtru2Wq+FkpqYtz pxkghlCD9FyIGQeePm2Ox1Plv413ycgo4D1YZ1lznMRZhECzv2 IH2FU1UIZBdynGaavOwIr4H/strY2sw+q4G9tGrwKTTwhDjwNK yRJDuD6z2cNS3hvci5bF1R3Ks/eG44DHadpOUbOW2t5XBmVIoB 4cE5iYagHbw2UivzPImLxQbBB3A== Cc: Marcel Ziswiler Subject: [U-Boot] [PATCH 01/10] arm: vf610: fix anadig register struct X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de The anadig_reg structure started at the wrong offset (fixed by adding resvA[4]), was missing some reserved field required for alignment purpose (resvB[3] between pll4_denom and pll6_ctrl) and further contained too short a reserved field causing further miss-alignment (resv10[7]). Discovered and tested by temporarily putting the following debug instrumentation into board_init(): struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; printf("&anadig->pll3_ctrl=0x%p\n", &anadig->pll3_ctrl); printf("&anadig->pll5_ctrl=0x%p\n", &anadig->pll5_ctrl); Signed-off-by: Marcel Ziswiler --- arch/arm/include/asm/arch-vf610/crm_regs.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 85f1fda..57a0242 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -55,6 +55,7 @@ struct ccm_reg { /* Analog components control digital interface (ANADIG) */ struct anadig_reg { + u32 resvA[4]; u32 pll3_ctrl; u32 resv0[3]; u32 pll7_ctrl; @@ -72,12 +73,13 @@ struct anadig_reg { u32 pll4_num; u32 resv7[3]; u32 pll4_denom; + u32 resvB[3]; u32 pll6_ctrl; u32 resv8[3]; u32 pll6_num; u32 resv9[3]; u32 pll6_denom; - u32 resv10[3]; + u32 resv10[7]; u32 pll5_ctrl; u32 resv11[3]; u32 pll3_pfd;