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[v2,1/2] riscv: Make RISCV_ACLINT visible

Message ID 7e80b87009b327aa618117baf223973e10c5b611.1777886786.git.michal.simek@amd.com
State New
Delegated to: Andes
Headers show
Series [v2,1/2] riscv: Make RISCV_ACLINT visible | expand

Commit Message

Michal Simek May 4, 2026, 9:26 a.m. UTC
A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced
Core Local Interruptor) hardware block.

Make RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with
prompts and enable them by default

Signed-off-by: Michal Simek <michal.simek@amd.com>
---

Changes in v2:
- Make symbols visible and disable them per platform basis

 arch/riscv/Kconfig | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

Comments

Michal Simek May 15, 2026, 12:06 p.m. UTC | #1
On 5/4/26 11:26, Michal Simek wrote:
> A platform (like Xilinx Microblaze V) does not have an ACLINT (Advanced
> Core Local Interruptor) hardware block.
> 
> Make RISCV_ACLINT and SPL_RISCV_ACLINT Kconfig symbols visible with
> prompts and enable them by default
> 
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> Changes in v2:
> - Make symbols visible and disable them per platform basis
> 
>   arch/riscv/Kconfig | 6 ++++--
>   1 file changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index ad7589123c6c..d14086e9f4dc 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -378,8 +378,9 @@ config DMA_ADDR_T_64BIT
>   	default y if 64BIT
>   
>   config RISCV_ACLINT
> -	bool
> +	bool "RISC-V ACLINT support"
>   	depends on RISCV_MMODE
> +	default y

This is breaking ae350_rv64_defconfig targets and likely others.
Default shouldn't be setup.

Anyway I will send v3 when CI ends.

Thanks,
Michal
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Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index ad7589123c6c..d14086e9f4dc 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -378,8 +378,9 @@  config DMA_ADDR_T_64BIT
 	default y if 64BIT
 
 config RISCV_ACLINT
-	bool
+	bool "RISC-V ACLINT support"
 	depends on RISCV_MMODE
+	default y
 	select REGMAP
 	select SYSCON
 	help
@@ -387,8 +388,9 @@  config RISCV_ACLINT
 	  associated with software and timer interrupts.
 
 config SPL_RISCV_ACLINT
-	bool
+	bool "RISC-V ACLINT support in SPL"
 	depends on SPL_RISCV_MMODE
+	default y
 	select SPL_REGMAP
 	select SPL_SYSCON
 	help