From patchwork Mon Jul 6 08:20:34 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 491463 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id B84D4140DBC for ; Mon, 6 Jul 2015 18:22:08 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 125344B6C6; Mon, 6 Jul 2015 10:21:57 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id R-LzOSqmlhxq; Mon, 6 Jul 2015 10:21:56 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 50F254B6B1; Mon, 6 Jul 2015 10:21:54 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C2CFD4B67B for ; Mon, 6 Jul 2015 10:21:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id XNp-3_Qv_r25 for ; Mon, 6 Jul 2015 10:21:51 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by theia.denx.de (Postfix) with ESMTPS id 8C76D4B62B for ; Mon, 6 Jul 2015 10:21:49 +0200 (CEST) Received: from localhost.localdomain ([46.140.72.82]) by mrelay.perfora.net (mreueus002) with ESMTPSA (Nemesis) id 0MEV9L-1ZERRD0WFN-00FiiJ; Mon, 06 Jul 2015 10:21:46 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Mon, 6 Jul 2015 10:20:34 +0200 Message-Id: <735c3c8ca0086dc0f5d8657baf3633bbcc4a22f2.1436170106.git.marcel.ziswiler@toradex.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: References: X-Provags-ID: V03:K0:j2N61Et/+KV4Nx9ZLzf3WR/5OggA8oacBi4jJNr9HEIo2rVgW/m RRJfqg1rUoo83+PZBFBEqH5iImKCwbsDORdxoJlyqX24kPkA3MZvNcJnSJXIBXzj60R7fSR K742ZpQHR8E81fI1OBSuwiSPGoh2flZCHSZvG7zUMNFKtb1C4GCp5PKAS53QKsW2f4UYWRL B2MbjGJUJl28Bx/e8Pmqw== X-UI-Out-Filterresults: notjunk:1; V01:K0:w+c0k9gKZhQ=:zTnKRagXiep93mj3t+TYsg XA4t8RvCFf1HrZan/3v7Y79Zw18c4n1VETIFYyaWS10klnn5sbjUWZ32CX0mVy54HKn5k+Dik Xrd+cfGrbQu51x8Fo7HjZx8ALHFtaQZ7m2vS8IpWlwjQKja7UFIvbcumKUaAoo30QkkQCexa8 epFj5qpEwMuklmC56VejkaRa8C5LhDL0hGS9FRV7PGeFfNVU80pWfxpIczakr8r8fzAW2XETB pJp1E4RVFA89R7o+b6zvesBgMRZq4xOL0MyymRzt/9vZRBFTO6wB8uOmtsndKO+lfrqIZxlaZ z3TCs3GsHBpT2WCa/kJ9dCCu9CwOLxKSD2/pzYKD8M1mewi6Wbf3QTa/kg1/1Thc8Mj+G3l9j f57KEJxFJPxTv8bGqx9jdcf6T9Me4jeL6aaNsG/zPAhyj55jx2MzHsZWnhYk9beZuYY+W+/2M v4LT3Tww1fMqx49wC+ZonevA7FeMaezGLCbpbfVjxuxDCHJKIVtF24SEv0RENezz6iyRZ544b xwCsv4sRQ+fNlHvg7ATSu8mQBHGLGEuqgy2wACsuaaxIYIPLqBBpuqq2oRZi9QIzm1v2vqP1V ZxaRjFuEoHqXlft5gQeRWe7hfT48c9poLwf8qtkE5kBj5s2jlBuUhm9AM4CZif78lHVzgMkiE YXc1+szPPzyWB4Uzj9A8GhOXc Cc: Stefan Agner , Tom Rini , Marcel Ziswiler , Tom Warren , Max Krummenacher , Scott Wood , Stephen Warren Subject: [U-Boot] [PATCH 08/13] tegra: nand: fix read_byte required for proper onfi detection X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command now required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late. While at it also disable subpage writes. Signed-off-by: Marcel Ziswiler --- drivers/mtd/nand/tegra_nand.c | 39 +++++++++------------------------------ 1 file changed, 9 insertions(+), 30 deletions(-) diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index b660f3b..9c90634 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -86,16 +86,6 @@ struct fdt_nand { struct nand_drv { struct nand_ctlr *reg; - - /* - * When running in PIO mode to get READ ID bytes from register - * RESP_0, we need this variable as an index to know which byte in - * register RESP_0 should be read. - * Because common code in nand_base.c invokes read_byte function two - * times for NAND_CMD_READID. - * And our controller returns 4 bytes at once in register RESP_0. - */ - int pio_byte_index; struct fdt_nand config; }; @@ -181,25 +171,16 @@ static int nand_waitfor_cmd_completion(struct nand_ctlr *reg) static uint8_t read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; - u32 dword_read; struct nand_drv *info; info = (struct nand_drv *)chip->priv; - /* In PIO mode, only 4 bytes can be transferred with single CMD_GO. */ - if (info->pio_byte_index > 3) { - info->pio_byte_index = 0; - writel(CMD_GO | CMD_PIO - | CMD_RX | CMD_CE0, - &info->reg->command); - if (!nand_waitfor_cmd_completion(info->reg)) - printf("Command timeout\n"); - } + writel(CMD_GO | CMD_PIO | CMD_RX | CMD_CE0 | CMD_A_VALID, + &info->reg->command); + if (!nand_waitfor_cmd_completion(info->reg)) + printf("Command timeout\n"); - dword_read = readl(&info->reg->resp); - dword_read = dword_read >> (8 * info->pio_byte_index); - info->pio_byte_index++; - return (uint8_t)dword_read; + return (uint8_t)readl(&info->reg->resp); } /** @@ -314,6 +295,9 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, if (column != -1 && (chip->options & NAND_BUSWIDTH_16)) column >>= 1; + /* Disable subpage writes as we do not provide ecc->hwctl */ + chip->options |= NAND_NO_SUBPAGE_WRITE; + nand_clear_interrupt_status(info->reg); /* Stop DMA engine, clear DMA completion status */ @@ -330,12 +314,8 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, case NAND_CMD_READID: writel(NAND_CMD_READID, &info->reg->cmd_reg1); writel(column & 0xFF, &info->reg->addr_reg1); - writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO - | CMD_RX | - ((4 - 1) << CMD_TRANS_SIZE_SHIFT) - | CMD_CE0, + writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0, &info->reg->command); - info->pio_byte_index = 0; break; case NAND_CMD_PARAM: writel(NAND_CMD_PARAM, &info->reg->cmd_reg1); @@ -376,7 +356,6 @@ static void nand_command(struct mtd_info *mtd, unsigned int command, | ((1 - 0) << CMD_TRANS_SIZE_SHIFT) | CMD_CE0, &info->reg->command); - info->pio_byte_index = 0; break; case NAND_CMD_RESET: writel(NAND_CMD_RESET, &info->reg->cmd_reg1);