From patchwork Fri Sep 7 12:50:48 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Joye X-Patchwork-Id: 182375 X-Patchwork-Delegate: afleming@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 4060C2C0086 for ; Fri, 7 Sep 2012 23:47:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 07B24282FB; Fri, 7 Sep 2012 15:47:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id jtVFIRrQNIqi; Fri, 7 Sep 2012 15:47:26 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 99B9D282FC; Fri, 7 Sep 2012 15:47:14 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8F2DB282FD for ; Fri, 7 Sep 2012 14:50:53 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PVd4Grn7dFG9 for ; Fri, 7 Sep 2012 14:50:52 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail.haslerrail.com (mail.haslerrail.com [212.103.73.117]) by theia.denx.de (Postfix) with ESMTP id 7EBB5282FC for ; Fri, 7 Sep 2012 14:50:49 +0200 (CEST) X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Date: Fri, 7 Sep 2012 14:50:48 +0200 Message-ID: <6670B5959A1255459E98630A607295B473CC2B@hrsrv31.haslerrail.net> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] powerpc mpc85xx: Do not protect TLB entry for debuggging in AS1 against invalidation Thread-Index: Ac2M92d2shcRJiG/Q6CKdsPmok216Q== From: "Joye Laurent" To: X-Mailman-Approved-At: Fri, 07 Sep 2012 15:47:08 +0200 Cc: afleming@gmail.com Subject: [U-Boot] [PATCH] powerpc mpc85xx: Do not protect TLB entry for debuggging in AS1 against invalidation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de In case of booting from RAM (CONFIG_SYS_RAMBOOT), a TLB entry is created for IVPR + IVOR15 to map on valid OP code address. This TLB entry shall not be protected against invalidation, because a new TLB entry to access RAM in AS0 will be created by cpu_init_early_f. If this TLB entry is protected against invalidation, this will creates 2 TLB for the same address range (forbidden). Signed-off-by: Laurent Joye --- arch/powerpc/cpu/mpc85xx/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 6aabc30..56c4ee7 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -229,8 +229,8 @@ l2_disabled: * TLB entry is created for IVPR + IVOR15 to map on valid OP code address * because "nexti" will resize TLB to 4K */ - lis r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@h - ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)@l + lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_256K)@h + ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_256K)@l lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_MONITOR_BASE, (MAS2_I))@h