| Message ID | 597714064e441f64c55d3e7f1adf656b81abb9e0.1612354721.git.michal.simek@xilinx.com |
|---|---|
| State | Superseded |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | clk: Add support to enable clocks | expand |
On Wed, Feb 3, 2021 at 2:18 PM Michal Simek <michal.simek@xilinx.com> wrote: > > From: T Karthik Reddy <t.karthik.reddy@xilinx.com> > > Enable rx clock along with tx clock for versal platform. > > Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/net/zynq_gem.c | 26 ++++++++++++++++++++------ > 1 file changed, 20 insertions(+), 6 deletions(-) > > diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c > index 5cb02bb3a7d2..ea080fbacc94 100644 > --- a/drivers/net/zynq_gem.c > +++ b/drivers/net/zynq_gem.c > @@ -205,7 +205,8 @@ struct zynq_gem_priv { > struct phy_device *phydev; > ofnode phy_of_node; > struct mii_dev *bus; > - struct clk clk; > + struct clk rx_clk; > + struct clk tx_clk; > u32 max_speed; > bool int_pcs; > bool dma_64bit; > @@ -476,18 +477,25 @@ static int zynq_gem_init(struct udevice *dev) > break; > } > > - ret = clk_set_rate(&priv->clk, clk_rate); > + ret = clk_set_rate(&priv->tx_clk, clk_rate); > if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { > dev_err(dev, "failed to set tx clock rate\n"); > return ret; > } > > - ret = clk_enable(&priv->clk); > - if (ret && ret != -ENOSYS) { > + ret = clk_enable(&priv->tx_clk); > + if (ret) { > dev_err(dev, "failed to enable tx clock\n"); > return ret; > } > > + if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { > + ret = clk_enable(&priv->rx_clk); > + if (ret) { > + dev_err(dev, "failed to enable rx clock\n"); > + return ret; > + } > + } > setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | > ZYNQ_GEM_NWCTRL_TXEN_MASK); > > @@ -694,9 +702,15 @@ static int zynq_gem_probe(struct udevice *dev) > priv->tx_bd = (struct emac_bd *)bd_space; > priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); > > - ret = clk_get_by_name(dev, "tx_clk", &priv->clk); > + ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk); > + if (ret < 0) { > + dev_err(dev, "failed to get tx_clock\n"); > + goto err1; > + } > + > + ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk); > if (ret < 0) { > - dev_err(dev, "failed to get clock\n"); > + dev_err(dev, "failed to get rx_clock\n"); > goto err1; > } > > -- > 2.30.0 > Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 5cb02bb3a7d2..ea080fbacc94 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -205,7 +205,8 @@ struct zynq_gem_priv { struct phy_device *phydev; ofnode phy_of_node; struct mii_dev *bus; - struct clk clk; + struct clk rx_clk; + struct clk tx_clk; u32 max_speed; bool int_pcs; bool dma_64bit; @@ -476,18 +477,25 @@ static int zynq_gem_init(struct udevice *dev) break; } - ret = clk_set_rate(&priv->clk, clk_rate); + ret = clk_set_rate(&priv->tx_clk, clk_rate); if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { dev_err(dev, "failed to set tx clock rate\n"); return ret; } - ret = clk_enable(&priv->clk); - if (ret && ret != -ENOSYS) { + ret = clk_enable(&priv->tx_clk); + if (ret) { dev_err(dev, "failed to enable tx clock\n"); return ret; } + if (IS_ENABLED(CONFIG_ARCH_VERSAL)) { + ret = clk_enable(&priv->rx_clk); + if (ret) { + dev_err(dev, "failed to enable rx clock\n"); + return ret; + } + } setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -694,9 +702,15 @@ static int zynq_gem_probe(struct udevice *dev) priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); - ret = clk_get_by_name(dev, "tx_clk", &priv->clk); + ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk); + if (ret < 0) { + dev_err(dev, "failed to get tx_clock\n"); + goto err1; + } + + ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk); if (ret < 0) { - dev_err(dev, "failed to get clock\n"); + dev_err(dev, "failed to get rx_clock\n"); goto err1; }