From patchwork Fri Mar 27 00:10:59 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iain Paton X-Patchwork-Id: 455244 X-Patchwork-Delegate: hdegoede@redhat.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 6989514012F for ; Fri, 27 Mar 2015 11:11:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=Y5oo3O4L; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CF325A742D; Fri, 27 Mar 2015 01:11:35 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OVoKDeeRfDbr; Fri, 27 Mar 2015 01:11:35 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37B84A7420; Fri, 27 Mar 2015 01:11:35 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E7DB3A7420 for ; Fri, 27 Mar 2015 01:11:31 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TJMxi3yvjLWs for ; Fri, 27 Mar 2015 01:11:31 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f179.google.com (mail-wi0-f179.google.com [209.85.212.179]) by theia.denx.de (Postfix) with ESMTPS id 9C7794B6CB for ; Fri, 27 Mar 2015 01:11:27 +0100 (CET) Received: by wibg7 with SMTP id g7so8184417wib.1 for ; Thu, 26 Mar 2015 17:11:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=message-id:date:from:user-agent:mime-version:to:cc:subject :content-type:content-transfer-encoding; bh=sqdEUu94aNzpw2x04GQqzmyaruJVsH9QJ9UCTR6qQJI=; b=Y5oo3O4LFzvzAd3gd6N6N94AWv5gVq6aH0g0iKfvcEIBN5oQ0lIVc4edMp7Fpo5Unr wTN/p9Aw2U8sgBkx/wItBdB9WJomnP143XIXLphO//XMDg6kMlS+9B9vhJbQzHkIYG7E T0CxfX7dBaJHcblRngNi/P2wsuGh28AbZDjcMfhzzMCofJWHKVJDhuiBugZ6o/q0trY1 JHCirEntiGw1W7XliYhLl1hMsLDXBultS4edu5aYSX6X9jbpmqF8JjUdrB9Wt9iePgKq CSyZcsJLoa0fxVGieKsfKHbXZ3njcAPoJetfGycUI5BsKGBvAb2bITNLLIIP0LliVpol zZrA== X-Received: by 10.180.76.148 with SMTP id k20mr52416747wiw.71.1427415087150; Thu, 26 Mar 2015 17:11:27 -0700 (PDT) Received: from [172.20.0.44] (hades.darkvoyage.org.uk. [81.187.177.1]) by mx.google.com with ESMTPSA id fo8sm455701wib.14.2015.03.26.17.11.25 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 26 Mar 2015 17:11:26 -0700 (PDT) Message-ID: <5514A013.7040300@gmail.com> Date: Fri, 27 Mar 2015 00:10:59 +0000 From: Iain Paton User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:16.0) Gecko/20121011 Thunderbird/16.0.1 MIME-Version: 1.0 To: Ian Campbell , Hans De Goede Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/3] sunxi: sun4i: add missing 912MHz clock divisors X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" clock divisors table was missing an entry for 912MHz. The same table is used for sun7i where the default boot clock is 912MHz, resulting in A20 boards being overclocked to 960MHz Signed-off-by: Iain Paton --- arch/arm/cpu/armv7/sunxi/clock_sun4i.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c index 49f4032..c720e96 100644 --- a/arch/arm/cpu/armv7/sunxi/clock_sun4i.c +++ b/arch/arm/cpu/armv7/sunxi/clock_sun4i.c @@ -102,6 +102,7 @@ static struct { /* This array must be ordered by frequency. */ { PLL1_CFG(16, 0, 0, 0), 384000000 }, { PLL1_CFG(16, 1, 0, 0), 768000000 }, + { PLL1_CFG(19, 1, 0, 0), 912000000 }, { PLL1_CFG(20, 1, 0, 0), 960000000 }, { PLL1_CFG(21, 1, 0, 0), 1008000000}, { PLL1_CFG(22, 1, 0, 0), 1056000000},