From patchwork Fri Jan 16 04:58:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joonyoung Shim X-Patchwork-Id: 429723 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 14CD21401B5 for ; Fri, 16 Jan 2015 15:58:29 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3D53C4B617; Fri, 16 Jan 2015 05:58:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id g6MuKbf38lCP; Fri, 16 Jan 2015 05:58:25 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB4474B610; Fri, 16 Jan 2015 05:58:25 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DC6144B60B for ; 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Fri, 16 Jan 2015 13:58:14 +0900 (KST) Received: from [10.252.81.123] by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NI900DXZ751Y290@mmp1.samsung.com>; Fri, 16 Jan 2015 13:58:13 +0900 (KST) Message-id: <54B89A79.2030205@samsung.com> Date: Fri, 16 Jan 2015 13:58:33 +0900 From: Joonyoung Shim User-Agent: Mozilla/5.0 (X11; Linux i686; rv:31.0) Gecko/20100101 Thunderbird/31.3.0 MIME-version: 1.0 To: Akshay Saraswat , u-boot@lists.denx.de References: <1421328674-15233-1-git-send-email-akshay.s@samsung.com> <1421328674-15233-4-git-send-email-akshay.s@samsung.com> In-reply-to: <1421328674-15233-4-git-send-email-akshay.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuplkeLIzCtJLcpLzFFi42JZI2JSpJs2a0eIwb6fnBan/jxmtLjxq43V ouNIC6PFty3bGC3e7u1kd2D1mN1wkcXj7J0djB59W1YxBjBHcdmkpOZklqUW6dslcGWse3GW vaDfpqLr50K2BsZegy5GTg4JAROJlqVX2CBsMYkL99YD2VwcQgJLGSVmPLrLDFN07sA5FojE IkaJ5WvaWCGc14wS3/pOsIBU8QpoSZxZthdsFIuAqsTDnz3sIDabgJ7EnW3HmUBsUYEwiYk3 H7NC1AtK/Jh8D6xXRMBBYtXGY2A2s4CTxMubxxhBbGEBP4mm591AcziAltVLvPtoDWJyCrhK vNgpAmIyA02/f1ELolFeYvOat8wgl0kIrGOX+PjvOSPENQIS3yYfYgGplxCQldh0AOotSYmD K26wTGAUm4XknlkIU2chmbqAkXkVo2hqQXJBcVJ6kbFecWJucWleul5yfu4mRmAsnf73rH8H 490D1ocYBTgYlXh4Gfy2hwixJpYVV+YeYjQFOmIis5Rocj4wYvNK4g2NzYwsTE1MjY3MLc2U xHkXSv0MFhJITyxJzU5NLUgtii8qzUktPsTIxMEp1cDoln1B/mmhn6/0h7mVP6dOnXrdYdPp iBfufBZd8qqT1zyYtOrPE5YJ3RmrmI8mzk6qDPBebyJ+Zt6hlTdTmxqOBm5Qv8pTPfHbXoP9 qx4clDTwV3H+v/WO6pv8uPBjEx223v50aPKHs78OF+477Gq/1sNLzy6VXdUg/+1un6yd7a8N ot8E8anmKbEUZyQaajEXFScCAIQ4/k2gAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrOIsWRmVeSWpSXmKPExsVy+t9jAd20WTtCDFZ2MVuc+vOY0eLGrzZW i44jLYwW37ZsY7R4u7eT3YHVY3bDRRaPs3d2MHr0bVnFGMAc1cBok5GamJJapJCal5yfkpmX bqvkHRzvHG9qZmCoa2hpYa6kkJeYm2qr5OIToOuWmQO0VEmhLDGnFCgUkFhcrKRvh2lCaIib rgVMY4Sub0gQXI+RARpIWMOYse7FWfaCfpuKrp8L2RoYew26GDk5JARMJM4dOMcCYYtJXLi3 nq2LkYtDSGARo8TyNW2sEM5rRolvfSfAqngFtCTOLNvLBmKzCKhKPPzZww5iswnoSdzZdpwJ xBYVCJOYePMxK0S9oMSPyffAekUEHCRWbTwGZjMLOEm8vHmMEcQWFvCTaHreDTSHA2hZvcS7 j9YgJqeAq8SLnSIgJjPQ9PsXtSAa5SU2r3nLPIFRYBaS+bMQqmYhqVrAyLyKUTS1ILmgOCk9 11CvODG3uDQvXS85P3cTIzhSn0ntYFzZYHGIUYCDUYmHl8Fve4gQa2JZcWXuIUYJDmYlEd7G 7h0hQrwpiZVVqUX58UWlOanFhxhNgb6fyCwlmpwPTCJ5JfGGxiZmRpZG5oYWRsbmSuK8SvZt IUIC6YklqdmpqQWpRTB9TBycUg2MUQ3ft2iceHMkXsd7+12ZW6avlgbNkvy64mTsOf7b/5O8 nnrrRi2V/7uL6ZTJQf25pgZeB+p03b96sS27ZHQppO7ng5ZuWY4A/zlSBTu3mZ/bq3SZ//ry GbNMFtmrJNa32+iHrtlh4HP1bNNCnT0tVUohNnsyxexMCtdKxrVarxIVS9sztaBdiaU4I9FQ i7moOBEAvgvaWeoCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Cc: jh80.chung@samsung.com Subject: Re: [U-Boot] [PATCH v2 3/6] Exynos542x: Add and enable get_periph_rate support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.13 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Hi, On 01/15/2015 10:31 PM, Akshay Saraswat wrote: > We planned to fetch peripheral rate through one generic API per > peripheral. These generic peripheral functions are in turn > expected to fetch apt values from a function refactored as > per SoC versions. This patch adds support for fetching peripheral > rates for Exynos5420 and Exynos5800. > > Signed-off-by: Akshay Saraswat > --- > Changes since v1: > - Changes suuport -> support in commit message. > - Removed position change of exynos5420_get_pll_clk. > - Removed #ifdef. > > arch/arm/cpu/armv7/exynos/clock.c | 151 +++++++++++++++++++++++++++++++-- > arch/arm/include/asm/arch-exynos/clk.h | 5 +- > 2 files changed, 148 insertions(+), 8 deletions(-) > > diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c > index 6a1b05f..1ef4f49 100644 > --- a/arch/arm/cpu/armv7/exynos/clock.c > +++ b/arch/arm/cpu/armv7/exynos/clock.c > @@ -27,7 +27,7 @@ struct clk_bit_info { > }; > > /* periph_id src_bit div_bit prediv_bit */ > -static struct clk_bit_info clk_bit_info[] = { > +static struct clk_bit_info exynos5_bit_info[] = { > {PERIPH_ID_UART0, 0, 0, -1}, > {PERIPH_ID_UART1, 4, 4, -1}, > {PERIPH_ID_UART2, 8, 8, -1}, > @@ -65,6 +65,44 @@ static struct clk_bit_info clk_bit_info[] = { > {PERIPH_ID_NONE, -1, -1, -1}, > }; > > +static struct clk_bit_info exynos542x_bit_info[] = { > + {PERIPH_ID_UART0, 4, 8, -1}, > + {PERIPH_ID_UART1, 8, 12, -1}, > + {PERIPH_ID_UART2, 12, 16, -1}, > + {PERIPH_ID_UART3, 16, 20, -1}, > + {PERIPH_ID_I2C0, -1, 8, -1}, > + {PERIPH_ID_I2C1, -1, 8, -1}, > + {PERIPH_ID_I2C2, -1, 8, -1}, > + {PERIPH_ID_I2C3, -1, 8, -1}, > + {PERIPH_ID_I2C4, -1, 8, -1}, > + {PERIPH_ID_I2C5, -1, 8, -1}, > + {PERIPH_ID_I2C6, -1, 8, -1}, > + {PERIPH_ID_I2C7, -1, 8, -1}, > + {PERIPH_ID_SPI0, 20, 20, 8}, > + {PERIPH_ID_SPI1, 24, 24, 16}, > + {PERIPH_ID_SPI2, 28, 28, 24}, > + {PERIPH_ID_SDMMC0, 0, 0, -1}, > + {PERIPH_ID_SDMMC1, 4, 10, -1}, > + {PERIPH_ID_SDMMC2, 8, 20, -1}, > + {PERIPH_ID_SDMMC3, -1, -1, -1}, > + {PERIPH_ID_I2C8, -1, 8, -1}, > + {PERIPH_ID_I2C9, -1, 8, -1}, > + {PERIPH_ID_I2S0, 0, 0, 4}, > + {PERIPH_ID_I2S1, 4, 12, 16}, > + {PERIPH_ID_SROMC, -1, -1, -1}, > + {PERIPH_ID_SPI3, 12, 16, 0}, > + {PERIPH_ID_SPI4, 16, 20, 8}, > + {PERIPH_ID_SDMMC4, 16, 0, 8}, > + {PERIPH_ID_PWM0, 24, 28, -1}, > + {PERIPH_ID_PWM1, 24, 28, -1}, > + {PERIPH_ID_PWM2, 24, 28, -1}, > + {PERIPH_ID_PWM3, 24, 28, -1}, > + {PERIPH_ID_PWM4, 24, 28, -1}, > + {PERIPH_ID_I2C10, -1, 8, -1}, > + > + {PERIPH_ID_NONE, -1, -1, -1}, > +}; > + > /* Epll Clock division values to achive different frequency output */ > static struct set_epll_con_val exynos5_epll_div[] = { > { 192000000, 0, 48, 3, 1, 0 }, > @@ -310,13 +348,19 @@ static unsigned long exynos542x_get_pll_clk(int pllreg) > static struct clk_bit_info *get_clk_bit_info(int peripheral) > { > int i; > + struct clk_bit_info *info; > > - for (i = 0; clk_bit_info[i].id != PERIPH_ID_NONE; i++) { > - if (clk_bit_info[i].id == peripheral) > + if (proid_is_exynos5420() || proid_is_exynos5800()) > + info = exynos542x_bit_info; > + else > + info = exynos5_bit_info; > + > + for (i = 0; info[i].id != PERIPH_ID_NONE; i++) { > + if (info[i].id == peripheral) > break; > } > > - return &clk_bit_info[i]; > + return &info[i]; > } > > static unsigned long exynos5_get_periph_rate(int peripheral) > @@ -415,12 +459,107 @@ static unsigned long exynos5_get_periph_rate(int peripheral) > return sub_clk; > } > > +static unsigned long exynos542x_get_periph_rate(int peripheral) > +{ > + struct clk_bit_info *bit_info = get_clk_bit_info(peripheral); > + unsigned long sclk, sub_clk; > + unsigned int src, div, sub_div = 0; > + struct exynos5420_clock *clk = > + (struct exynos5420_clock *)samsung_get_base_clock(); > + > + switch (peripheral) { > + case PERIPH_ID_UART0: > + case PERIPH_ID_UART1: > + case PERIPH_ID_UART2: > + case PERIPH_ID_UART3: > + src = readl(&clk->src_peric0); > + div = readl(&clk->div_peric0); > + break; > + case PERIPH_ID_PWM0: > + case PERIPH_ID_PWM1: > + case PERIPH_ID_PWM2: > + case PERIPH_ID_PWM3: > + case PERIPH_ID_PWM4: > + src = readl(&clk->src_peric0); > + div = readl(&clk->div_peric0); > + break; UARTx and PWMx use same register, so you can remove duplicated codes. > + case PERIPH_ID_SPI0: > + case PERIPH_ID_SPI1: > + case PERIPH_ID_SPI2: > + src = readl(&clk->src_peric1); > + div = readl(&clk->div_peric1); > + sub_div = readl(&clk->div_peric4); > + break; > + case PERIPH_ID_SPI3: > + case PERIPH_ID_SPI4: > + src = readl(&clk->src_isp); > + div = readl(&clk->div_isp1); > + sub_div = readl(&clk->div_isp1); > + break; > + case PERIPH_ID_SDMMC0: > + case PERIPH_ID_SDMMC1: > + case PERIPH_ID_SDMMC2: > + case PERIPH_ID_SDMMC3: > + src = readl(&clk->src_fsys); > + div = readl(&clk->div_fsys1); > + break; > + case PERIPH_ID_I2C0: > + case PERIPH_ID_I2C1: > + case PERIPH_ID_I2C2: > + case PERIPH_ID_I2C3: > + case PERIPH_ID_I2C4: > + case PERIPH_ID_I2C5: > + case PERIPH_ID_I2C6: > + case PERIPH_ID_I2C7: > + case PERIPH_ID_I2C8: > + case PERIPH_ID_I2C9: > + case PERIPH_ID_I2C10: > + sclk = exynos542x_get_pll_clk(MPLL); > + sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) > + & 0x7) + 1; > + return sclk / sub_div; > + default: > + debug("%s: invalid peripheral %d", __func__, peripheral); > + return -1; > + }; > + > + src = (src >> bit_info->src_bit) & 0xf; > + > + switch (src) { > + case EXYNOS542x_SRC_MPLL: > + sclk = exynos542x_get_pll_clk(MPLL); > + break; > + case EXYNOS542x_SRC_EPLL: > + sclk = exynos542x_get_pll_clk(EPLL); > + break; > + case EXYNOS542x_SRC_RPLL: > + sclk = exynos542x_get_pll_clk(RPLL); > + break; > + default: > + return 0; > + } > + > + /* Ratio clock division for this peripheral */ > + div = (div >> bit_info->div_bit) & 0xf; > + sub_clk = sclk / (div + 1); > + > + if (bit_info->prediv_bit >= 0) { > + sub_div = (sub_div >> bit_info->prediv_bit) & 0xff; > + return sub_clk / (sub_div + 1); > + } > + > + return sub_clk; > +} > + > unsigned long clock_get_periph_rate(int peripheral) > { > - if (cpu_is_exynos5()) > + if (cpu_is_exynos5()) { > + if (proid_is_exynos5420() || proid_is_exynos5800()) > + return exynos542x_get_periph_rate(peripheral); > return exynos5_get_periph_rate(peripheral); > - else > + } else { > return 0; > + } > } > > /* exynos4: return ARM clock frequency */ > diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h > index db24dc0..606b3ef 100644 > --- a/arch/arm/include/asm/arch-exynos/clk.h > +++ b/arch/arm/include/asm/arch-exynos/clk.h > @@ -23,8 +23,9 @@ > #define SET_RATIO(x, y) ((y & 0xf) << (x << 4)) > > enum pll_src_bit { > - EXYNOS_SRC_MPLL = 6, > - EXYNOS_SRC_EPLL, > + EXYNOS542x_SRC_MPLL = 3, > + EXYNOS_SRC_MPLL = EXYNOS542x_SRC_EPLL = 6, > + EXYNOS_SRC_EPLL = EXYNOS542x_SRC_RPLL, > EXYNOS_SRC_VPLL, > }; Could you use one item by one line like below? Thanks. diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index db24dc0..da9bfcd 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -26,6 +26,9 @@ enum pll_src_bit { EXYNOS_SRC_MPLL = 6, EXYNOS_SRC_EPLL, EXYNOS_SRC_VPLL, + EXYNOS542x_SRC_MPLL = 3, + EXYNOS542x_SRC_EPLL = 6, + EXYNOS542x_SRC_RPLL, }; unsigned long get_pll_clk(int pllreg);