| Message ID | 52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com |
|---|---|
| State | Accepted |
| Commit | 13622c7a9dfabb2dd07e8c125243f47540673ba9 |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | [1/2] arm64: zynqmp: Describe TI phy as ethernet-phy-id | expand |
On 9/9/22 13:05, Michal Simek wrote: > TI DP83867 is using strapping based on MIO pins. Tristate setup can influce > PHY address. That's why switch description with ethernet-phy-id compatible > string which enable calling reset. PHY itself setups phy address after > power up or reset. Reset description will be added in separate commit. > > Signed-off-by: Michal Simek <michal.simek@amd.com> > --- > > arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++++------- > arch/arm/dts/zynqmp-zcu104-revA.dts | 18 ++++++++++++------ > arch/arm/dts/zynqmp-zcu104-revC.dts | 18 ++++++++++++------ > arch/arm/dts/zynqmp-zcu111-revA.dts | 18 ++++++++++++------ > arch/arm/dts/zynqmp-zcu208-revA.dts | 18 ++++++++++++------ > arch/arm/dts/zynqmp-zcu216-revA.dts | 19 ++++++++++++------- > 6 files changed, 73 insertions(+), 38 deletions(-) > > diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts > index 71c3dde4bf21..f04bc9969bd0 100644 > --- a/arch/arm/dts/zynqmp-zcu102-revA.dts > +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts > @@ -217,13 +217,19 @@ > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@21 { > - reg = <21>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@21 { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <21>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ > + }; > }; > }; > > diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts > index 1418cffb2042..6df9a1343859 100644 > --- a/arch/arm/dts/zynqmp-zcu104-revA.dts > +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts > @@ -109,12 +109,18 @@ > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > }; > }; > > diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts > index 7fd19ca3a8c0..0721516bd109 100644 > --- a/arch/arm/dts/zynqmp-zcu104-revC.dts > +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts > @@ -114,12 +114,18 @@ > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > }; > }; > > diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts > index e412992ff1bd..c37c4b8b6177 100644 > --- a/arch/arm/dts/zynqmp-zcu111-revA.dts > +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts > @@ -172,12 +172,18 @@ > phy-mode = "rgmii-id"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_gem3_default>; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > }; > }; > > diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts > index c5cdd58af6ed..3e8ee429eb79 100644 > --- a/arch/arm/dts/zynqmp-zcu208-revA.dts > +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts > @@ -169,12 +169,18 @@ > status = "okay"; > phy-handle = <&phy0>; > phy-mode = "rgmii-id"; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > }; > }; > > diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts > index caae16965d6f..80e7ddb97080 100644 > --- a/arch/arm/dts/zynqmp-zcu216-revA.dts > +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts > @@ -176,15 +176,20 @@ > status = "okay"; > phy-handle = <&phy0>; > phy-mode = "rgmii-id"; > - phy0: ethernet-phy@c { > - reg = <0xc>; > - ti,rx-internal-delay = <0x8>; > - ti,tx-internal-delay = <0xa>; > - ti,fifo-depth = <0x1>; > - ti,dp83867-rxctrl-strap-quirk; > + mdio: mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + phy0: ethernet-phy@c { > + #phy-cells = <1>; > + compatible = "ethernet-phy-id2000.a231"; > + reg = <0xc>; > + ti,rx-internal-delay = <0x8>; > + ti,tx-internal-delay = <0xa>; > + ti,fifo-depth = <0x1>; > + ti,dp83867-rxctrl-strap-quirk; > + }; > }; > }; > - > &gpio { > status = "okay"; > gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */ Applied both. M
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 71c3dde4bf21..f04bc9969bd0 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -217,13 +217,19 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; - /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@21 { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */ + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 1418cffb2042..6df9a1343859 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -109,12 +109,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index 7fd19ca3a8c0..0721516bd109 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -114,12 +114,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index e412992ff1bd..c37c4b8b6177 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -172,12 +172,18 @@ phy-mode = "rgmii-id"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem3_default>; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index c5cdd58af6ed..3e8ee429eb79 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -169,12 +169,18 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index caae16965d6f..80e7ddb97080 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -176,15 +176,20 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - phy0: ethernet-phy@c { - reg = <0xc>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - ti,dp83867-rxctrl-strap-quirk; + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + phy0: ethernet-phy@c { + #phy-cells = <1>; + compatible = "ethernet-phy-id2000.a231"; + reg = <0xc>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + ti,dp83867-rxctrl-strap-quirk; + }; }; }; - &gpio { status = "okay"; gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce PHY address. That's why switch description with ethernet-phy-id compatible string which enable calling reset. PHY itself setups phy address after power up or reset. Reset description will be added in separate commit. Signed-off-by: Michal Simek <michal.simek@amd.com> --- arch/arm/dts/zynqmp-zcu102-revA.dts | 20 +++++++++++++------- arch/arm/dts/zynqmp-zcu104-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu104-revC.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu111-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu208-revA.dts | 18 ++++++++++++------ arch/arm/dts/zynqmp-zcu216-revA.dts | 19 ++++++++++++------- 6 files changed, 73 insertions(+), 38 deletions(-)