diff mbox series

[1/4] mtd: spi-nor-core: Default to addr_width of 3 for configurable widths

Message ID 4b8388a9961cac4024647228f12a3da24b338081.1662011338.git.Takahiro.Kuwano@infineon.com
State Accepted
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series mtd: spi-nor-core: Track flash's internal address mode in s25hx-t | expand

Commit Message

Takahiro Kuwano Sept. 1, 2022, 6:05 a.m. UTC 
From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>

JESD216D-01 mentions that "defaults to 3-Byte mode; enters 4-Byte mode on
command."

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
---
 drivers/mtd/spi/spi-nor-core.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e3c86e080a..90d0f769f0 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2213,6 +2213,7 @@  static int spi_nor_parse_bfpt(struct spi_nor *nor,
 	/* Number of address bytes. */
 	switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
 	case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY:
+	case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4:
 		nor->addr_width = 3;
 		break;