From patchwork Mon Nov 5 20:12:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Beno=C3=AEt_Th=C3=A9baudeau?= X-Patchwork-Id: 197285 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 691E32C00A8 for ; Tue, 6 Nov 2012 07:05:56 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 27FF44A365; Mon, 5 Nov 2012 21:05:55 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZZe27AwvXxU5; Mon, 5 Nov 2012 21:05:54 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 5A4334A3A4; Mon, 5 Nov 2012 21:05:53 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4EE394A3A4 for ; Mon, 5 Nov 2012 21:05:51 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2y-IUq3jvihA for ; Mon, 5 Nov 2012 21:05:50 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from zose-mta11.web4all.fr (zose-mta-11.w4a.fr [178.33.204.86]) by theia.denx.de (Postfix) with ESMTP id 0C7254A365 for ; Mon, 5 Nov 2012 21:05:48 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 1444E46051; Mon, 5 Nov 2012 21:12:15 +0100 (CET) X-Virus-Scanned: amavisd-new at zose1.web4all.fr Received: from zose-mta11.web4all.fr ([127.0.0.1]) by localhost (zose-mta11.web4all.fr [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 65twaKdx1-JY; Mon, 5 Nov 2012 21:12:14 +0100 (CET) Received: from zose-store12.web4all.fr (zose-store12.web4all.fr [178.33.204.49]) by zose-mta11.web4all.fr (Postfix) with ESMTP id 81BD04600F; Mon, 5 Nov 2012 21:12:14 +0100 (CET) Date: Mon, 5 Nov 2012 21:12:15 +0100 (CET) From: =?utf-8?Q?Beno=C3=AEt_Th=C3=A9baudeau?= To: U-Boot-Users ML Message-ID: <450214918.587357.1352146335113.JavaMail.root@advansee.com> In-Reply-To: <412111025.587245.1352146184216.JavaMail.root@advansee.com> MIME-Version: 1.0 X-Originating-IP: [88.188.188.98] X-Mailer: Zimbra 7.2.0_GA_2669 (ZimbraWebClient - FF3.0 (Win)/7.2.0_GA_2669) Cc: Marek Vasut Subject: [U-Boot] [PATCH 08/13] ehci-mxc: Make EHCI power/oc polarities configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Make EHCI power and overcurrent polarities configurable. If not set, these new configurartions keep the default register values so that existing board files do not have to be changed. Signed-off-by: Benoît Thébaudeau Cc: Marek Vasut Cc: Stefano Babic --- .../drivers/usb/host/ehci-mx5.c | 51 ++++++++++++++++++++ .../include/usb/ehci-fsl.h | 10 ++-- 2 files changed, 57 insertions(+), 4 deletions(-) diff --git u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c index 7da1398..52aeae5 100644 --- u-boot-usb-76454b2.orig/drivers/usb/host/ehci-mx5.c +++ u-boot-usb-76454b2/drivers/usb/host/ehci-mx5.c @@ -44,24 +44,33 @@ /* USB_CTRL */ #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ #define MXC_OTG_UCTRL_OPM_BIT (1 << 24) /* OTG power mask */ +#define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24) /* OTG power pin polarity */ #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12) /* Host1 ULPI interrupt enable */ #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11) /* HOST1 wakeup intr enable */ #define MXC_H1_UCTRL_H1PM_BIT (1 << 8) /* HOST1 power mask */ +#define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8) /* HOST1 power pin polarity */ /* USB_PHY_CTRL_FUNC */ +#define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9) /* OTG Polarity of Overcurrent */ #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ +#define MXC_H1_OC_POL_BIT (1 << 6) /* UH1 Polarity of Overcurrent */ #define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ +#define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3) /* OTG Power Pin Polarity */ /* USBH2CTRL */ +#define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31) #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30) #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8) #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7) #define MXC_H2_UCTRL_H2PM_BIT (1 << 4) +#define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4) /* USBH3CTRL */ +#define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31) #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30) #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8) #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7) +#define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4) /* USB_CTRL_1 */ #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25) @@ -151,12 +160,22 @@ int mxc_set_usbcontrol(int port, unsigned int flags) if (flags & MXC_EHCI_INTERNAL_PHY) { v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_OTG_PHYCTRL_OC_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) /* OC/USBPWR is used */ v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT; else /* OC/USBPWR is not used */ v |= MXC_OTG_PHYCTRL_OC_DIS_BIT; +#ifdef CONFIG_MX51 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_OTG_PHYCTRL_PWR_POL_BIT; + else + v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); @@ -167,6 +186,12 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_OTG_UCTRL_OPM_BIT; #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_OTG_UCTRL_O_PWR_POL_BIT; + else + v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); } break; @@ -186,9 +211,19 @@ int mxc_set_usbcontrol(int port, unsigned int flags) else v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used */ #endif +#ifdef CONFIG_MX53 + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H1_UCTRL_H1_PWR_POL_BIT; + else + v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT; +#endif __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H1_OC_POL_BIT; + else + v &= ~MXC_H1_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */ else @@ -205,10 +240,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags) v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used */ #endif #ifdef CONFIG_MX53 + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H2_UCTRL_H2_OC_POL_BIT; + else + v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */ else v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */ + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H2_UCTRL_H2_PWR_POL_BIT; + else + v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT; #endif __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET); @@ -216,10 +259,18 @@ int mxc_set_usbcontrol(int port, unsigned int flags) #ifdef CONFIG_MX53 case 3: /* Host 3 ULPI */ v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); + if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW) + v |= MXC_H3_UCTRL_H3_OC_POL_BIT; + else + v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT; if (flags & MXC_EHCI_POWER_PINS_ENABLED) v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */ else v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */ + if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH) + v |= MXC_H3_UCTRL_H3_PWR_POL_BIT; + else + v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT; __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET); break; diff --git u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h u-boot-usb-76454b2/include/usb/ehci-fsl.h index 4dee5b0..a1438d6 100644 --- u-boot-usb-76454b2.orig/include/usb/ehci-fsl.h +++ u-boot-usb-76454b2/include/usb/ehci-fsl.h @@ -266,11 +266,13 @@ struct usb_ehci { #define MXC_EHCI_INTERFACE_MASK (0xf) #define MXC_EHCI_POWER_PINS_ENABLED (1 << 5) -#define MXC_EHCI_TTL_ENABLED (1 << 6) +#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH (1 << 6) +#define MXC_EHCI_OC_PIN_ACTIVE_LOW (1 << 7) +#define MXC_EHCI_TTL_ENABLED (1 << 8) -#define MXC_EHCI_INTERNAL_PHY (1 << 7) -#define MXC_EHCI_IPPUE_DOWN (1 << 8) -#define MXC_EHCI_IPPUE_UP (1 << 9) +#define MXC_EHCI_INTERNAL_PHY (1 << 9) +#define MXC_EHCI_IPPUE_DOWN (1 << 10) +#define MXC_EHCI_IPPUE_UP (1 << 11) /* Board-specific initialization */ int board_ehci_hcd_init(int port);