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bh=++CS0uuA4OyILFkLHWiJ9CfrYmJnM+xjMf+vtfxhqXw=; b=E2tjZTiJdwVDj/iGPMa1P//Fnrm9qyIGOR3MO4RLiYYv8zBz9JkDUwUKeXV0VlcDRS y4erCOVv0WBOUju2LWh25U4I2Ef08aMaEU7SJQXjd696pP9ugQH2k0GoKaofPSGQ6zMh iJF99GAhiqQL0I6GM9lN6bQVKp5kvnBKQs5qiG5lO8s7gQJokZLru5hVNcUUIMP43mwY BlKYNxdjG/2QXZpYLdqoxjjSYlrOuJKEn8fhIp70OyNC8wtyN4N2J0HRA069LYa+k1WD A82C5KloanGpVnvt7e3UJP60aDXErzkLX6gn+AL0kJEiRbKFjlKZQmdIQz2aT1OVg56x y5dw== X-Gm-Message-State: AOAM53153zVRePMWkKiBlz7yIOypTnWhvCj0DNqIWN4+ZJfDs3DO5pUV Qp1JWNyGGqiwxHUK8eFHuhFra2vJr9PLFmiK X-Google-Smtp-Source: ABdhPJwOJUe7WmrA5B9YU8TfAi1IldcLFgpm0LTg4lkBM9Chql+jmo6byCZRZq3x/Dph3iL4j5vYBA== X-Received: by 2002:adf:deca:: with SMTP id i10mr27090235wrn.344.1624261411059; Mon, 21 Jun 2021 00:43:31 -0700 (PDT) Received: from localhost ([2a02:768:2307:40d6::f9e]) by smtp.gmail.com with ESMTPSA id 9sm7650712wmf.3.2021.06.21.00.43.30 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 21 Jun 2021 00:43:30 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de, git@xilinx.com Cc: Piyush Mehta Subject: [PATCH] arm64: dts: zynqmp: Add psgtr and phy entry for USB and SATA node Date: Mon, 21 Jun 2021 09:43:25 +0200 Message-Id: <3208795efe0257f20a40c3d13c87175e226ec89a.1624261401.git.michal.simek@xilinx.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean From: Piyush Mehta This patch adds psgtr clocks and phy entry for USB0, USB1 and SATA node for zc1751-xm017-dc3 board. Signed-off-by: Piyush Mehta Signed-off-by: Michal Simek --- arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index a9bac1dec03e..344323ab7f93 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -11,6 +11,7 @@ #include "zynqmp.dtsi" #include "zynqmp-clk-ccf.dtsi" +#include / { model = "ZynqMP zc1751-xm017-dc3 RevA"; @@ -37,6 +38,18 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + clock_si5338_2: clk26 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + clock_si5338_3: clk125 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; }; &fpd_dma_chan1 { @@ -166,6 +179,13 @@ }; }; +&psgtr { + status = "okay"; + /* usb3, sata */ + clocks = <&clock_si5338_2>, <&clock_si5338_3>; + clock-names = "ref2", "ref3"; +}; + &rtc { status = "okay"; }; @@ -181,6 +201,8 @@ ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>; ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + phy-names = "sata-phy"; + phys = <&psgtr 2 PHY_TYPE_SATA 0 3>; }; &sdhci1 { /* emmc with some settings */ @@ -205,6 +227,8 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 0 PHY_TYPE_USB3 0 2>; maximum-speed = "super-speed"; }; @@ -217,5 +241,7 @@ status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; + phy-names = "usb3-phy"; + phys = <&psgtr 3 PHY_TYPE_USB3 1 2>; maximum-speed = "super-speed"; };