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[05/10] riscv: andes: Add Kconfig option for Andes erratum #35102

Message ID 20261002-mt2824-v1-5-bc44cf0e0289@bootlin.com
State Under Review
Delegated to: Tim Ouyang
Headers show
Series riscv: Add support for Metanoia MT2824 SoC and MT5824 EVB | expand

Commit Message

Benoît Monin Oct. 2, 2026, 1:02 p.m. UTC 
From: Jun Chang <jun.chang@metanoia-comm.com>

Add the ANDES_ERRATA_35102 config option to control the workaround for
Andes CPU erratum #35102. When enabled, non-blocking load is disabled in
the MMISC_CTL register during harts_early_init() to prevent potential
data corruption.

Signed-off-by: Jun Chang <jun.chang@metanoia-comm.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/riscv/cpu/andes/Kconfig | 3 +++
 arch/riscv/cpu/andes/cpu.c   | 7 ++++++-
 2 files changed, 9 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/riscv/cpu/andes/Kconfig b/arch/riscv/cpu/andes/Kconfig
index 120fec5e540..a2e68b6ad9c 100644
--- a/arch/riscv/cpu/andes/Kconfig
+++ b/arch/riscv/cpu/andes/Kconfig
@@ -15,3 +15,6 @@  config RISCV_ANDES
 	help
 	  Run U-Boot on AndeStar V5 platforms and use some specific features
 	  which are provided by Andes Technology AndeStar V5 families.
+
+config ANDES_ERRATA_35102
+	bool
diff --git a/arch/riscv/cpu/andes/cpu.c b/arch/riscv/cpu/andes/cpu.c
index d25ecba0e88..44704a2359e 100644
--- a/arch/riscv/cpu/andes/cpu.c
+++ b/arch/riscv/cpu/andes/cpu.c
@@ -57,7 +57,12 @@  void harts_early_init(void)
 			}
 		}
 
-		mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+		if (IS_ENABLED(CONFIG_ANDES_ERRATA_35102)) {
+			/* Errata #35102: Disable non-blocking load */
+			mmisc_ctl_val &= ~MMISC_CTL_NON_BLOCKING_EN;
+		} else {
+			mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN;
+		}
 
 		csr_write(CSR_MMISC_CTL, mmisc_ctl_val);
 	}