@@ -119,6 +119,15 @@ config TARGET_MT8365
It is including UART, SPI, USB2.0 dual role, SD and MMC cards, NAND, PWM,
I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+config TARGET_MT8366
+ bool "MediaTek MT8366 SoC"
+ select ARM64
+ help
+ The MediaTek MT8366 is a ARM64-based SoC with a single-core Cortex-A76 and
+ a five-core Cortex-A55. It is including UART, SPI, USB3.0 dual role,
+ SD and MMC cards, PWM, I2C, I2S, S/PDIF, and several LPDDR4x
+ options.
+
config TARGET_MT8512
bool "MediaTek MT8512 SoC"
select ARM64
@@ -159,6 +168,7 @@ config MTK_MEM_MAP_DDR_BASE_PHY
config MTK_MEM_MAP_DDR_SIZE
hex "DDR .size in mem_map"
default 0x200000000 if TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8188 || TARGET_MT8195
+ default 0x100000000 if TARGET_MT8366
default 0xc0000000 if TARGET_MT8365
default 0x80000000 if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT8183
default 0x40000000 if TARGET_MT7622 || TARGET_MT8512
@@ -207,7 +217,7 @@ config SYS_CONFIG_NAME
config MTK_BROM_HEADER_INFO
string
default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8189 || TARGET_MT8195
+ default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8366 || TARGET_MT8183 || TARGET_MT8188 || TARGET_MT8189 || TARGET_MT8195
default "lk=1" if TARGET_MT7623
config MTK_TZ_MOVABLE
@@ -17,6 +17,7 @@ obj-$(CONFIG_TARGET_MT8188) += mt8188/
obj-$(CONFIG_TARGET_MT8189) += mt8189/
obj-$(CONFIG_TARGET_MT8195) += mt8195/
obj-$(CONFIG_TARGET_MT8365) += mt8365/
+obj-$(CONFIG_TARGET_MT8366) += mt8366/
obj-$(CONFIG_TARGET_MT8512) += mt8512/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
obj-$(CONFIG_TARGET_MT8518) += mt8518/
@@ -39,7 +39,8 @@ void enable_caches(void)
u32 mediatek_sip_part_name(void)
{
if (CONFIG_IS_ENABLED(TARGET_MT8188) || CONFIG_IS_ENABLED(TARGET_MT8189) ||
- CONFIG_IS_ENABLED(TARGET_MT8195) || CONFIG_IS_ENABLED(TARGET_MT8365)) {
+ CONFIG_IS_ENABLED(TARGET_MT8195) || CONFIG_IS_ENABLED(TARGET_MT8365) ||
+ CONFIG_IS_ENABLED(TARGET_MT8366)) {
struct arm_smccc_res res __maybe_unused;
arm_smccc_smc(MTK_SIP_PLAT_BINFO, 0, 0, 0, 0, 0, 0, 0, &res);
new file mode 100644
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-y += init.o
new file mode 100644
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Baylibre, SAS
+ * Copyright (C) 2026 MediaTek Inc.
+ * Author: Chris Chen <chris-qj.chen@mediatek.com>
+ */
+
+#include <fdtdec.h>
+#include <stdio.h>
+#include <asm/global_data.h>
+#include <asm/system.h>
+#include <dm/uclass.h>
+#include <linux/kernel.h>
+#include <linux/sizes.h>
+#include <wdt.h>
+
+#include "../cpu.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
+{
+ /*
+ * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like
+ * MMC requires DMA buffer allocated below SZ_4G.
+ */
+ return min(gd->ram_top, SZ_4G);
+}
+
+void reset_cpu(void)
+{
+ if (CONFIG_IS_ENABLED(PSCI_RESET)) {
+ psci_system_reset();
+ } else {
+ struct udevice *wdt;
+
+ uclass_first_device(UCLASS_WDT, &wdt);
+ if (wdt)
+ wdt_expire_now(wdt, 0);
+ }
+}
+
+int print_cpuinfo(void)
+{
+ u32 part = mediatek_sip_part_name();
+
+ if (part)
+ printf("CPU: MediaTek MT%.4x\n", part);
+ else
+ printf("CPU: MediaTek MT8366 series\n");
+
+ return 0;
+}