diff mbox series

[v4,03/14] configs: k1: enable early timer support

Message ID 20260519-b4-k1-spl-bring-up-v4-3-3915a2a904c1@riscstar.com
State New
Delegated to: Andes
Headers show
Series riscv: spacemit: k1: add SPL support | expand

Commit Message

Guodong Xu May 19, 2026, 10:26 a.m. UTC 
From: Raymond Mao <raymond.mao@riscstar.com>

Enable CONFIG_TIMER_EARLY to allow udelay() calls during
early initialization phases. This is required for proper
timing operations before the full timer driver is available.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
Signed-off-by: Guodong Xu <guodong@riscstar.com>

---
v4:
- SPL_RISCV_MMODE (not SMODE); disable SPL SMP.
- Add RISCV_MMODE_TIMERBASE/_TIMEROFF.
- Enable SPL_REGMAP/SPL_SYSCON.
---
 configs/spacemit_k1_defconfig | 6 +++++-
 include/configs/k1.h          | 5 +++++
 2 files changed, 10 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/configs/spacemit_k1_defconfig b/configs/spacemit_k1_defconfig
index 29050ece278..fd0d228992a 100644
--- a/configs/spacemit_k1_defconfig
+++ b/configs/spacemit_k1_defconfig
@@ -17,9 +17,10 @@  CONFIG_DEBUG_UART_CLOCK=14700000
 CONFIG_TARGET_SPACEMIT_K1=y
 CONFIG_ARCH_RV64I=y
 CONFIG_RISCV_SMODE=y
+CONFIG_SPL_RISCV_MMODE=y
+# CONFIG_SPL_SMP is not set
 CONFIG_STACK_SIZE=0x100000
 CONFIG_FIT=y
-CONFIG_SPL_FIT_SIGNATURE=y
 CONFIG_SUPPORT_RAW_INITRD=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_CBSIZE=256
@@ -31,6 +32,8 @@  CONFIG_SPL_HAVE_INIT_STACK=y
 CONFIG_HUSH_PARSER=y
 CONFIG_OF_UPSTREAM=y
 CONFIG_ENV_OVERWRITE=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
 CONFIG_CLK_SPACEMIT=y
 CONFIG_CLK_SPACEMIT_K1=y
 CONFIG_PINCTRL=y
@@ -40,3 +43,4 @@  CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_DEBUG_UART_ANNOUNCE=y
 CONFIG_SYS_NS16550=y
 CONFIG_SYS_NS16550_MEM32=y
+CONFIG_TIMER_EARLY=y
diff --git a/include/configs/k1.h b/include/configs/k1.h
index 15a40f2128f..e09c3594905 100644
--- a/include/configs/k1.h
+++ b/include/configs/k1.h
@@ -12,4 +12,9 @@ 
 #define CFG_SYS_NS16550_IER	    0x40 /* UART Unit Enable */
 #define CFG_SYS_SDRAM_BASE	    0x0
 
+#define RISCV_MMODE_TIMERBASE	    0xe4000000
+#define RISCV_MMODE_TIMEROFF	    0xbff8
+#define RISCV_MMODE_TIMER_FREQ	    24000000
+#define RISCV_SMODE_TIMER_FREQ	    24000000
+
 #endif /* __CONFIG_H */