diff mbox series

[10/16] dts: k1: add QSPI controller support

Message ID 20260422143112.1329478-11-raymondmaoca@gmail.com
State New
Delegated to: Andes
Headers show
Series Add PIN and SPI support for Spacemit K1 | expand

Commit Message

Raymond Mao April 22, 2026, 2:31 p.m. UTC 
From: Raymond Mao <raymond.mao@riscstar.com>

Add QSPI controller support in DTS for Spacemit K1 SoC.

Signed-off-by: Raymond Mao <raymond.mao@riscstar.com>
---
 arch/riscv/dts/k1-spl.dts | 15 +++++++++++++++
 arch/riscv/dts/k1.dtsi    | 16 ++++++++++++++++
 2 files changed, 31 insertions(+)
diff mbox series

Patch

diff --git a/arch/riscv/dts/k1-spl.dts b/arch/riscv/dts/k1-spl.dts
index 6f9407aada6..e3311af76e6 100644
--- a/arch/riscv/dts/k1-spl.dts
+++ b/arch/riscv/dts/k1-spl.dts
@@ -226,3 +226,18 @@ 
 		};
 	};
 };
+
+&qspi {
+	status = "okay";
+	bootph-pre-ram;
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <26500000>;
+		m25p,fast-read;
+		broken-flash-reset;
+		status = "okay";
+		bootph-pre-ram;
+	};
+};
diff --git a/arch/riscv/dts/k1.dtsi b/arch/riscv/dts/k1.dtsi
index fc3a693a10e..96f604b0561 100644
--- a/arch/riscv/dts/k1.dtsi
+++ b/arch/riscv/dts/k1.dtsi
@@ -879,6 +879,22 @@ 
 				status = "disabled";
 			};
 
+			qspi: spi@d420c000 {
+				compatible = "spacemit,k1-qspi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				reg = <0x0 0xd420c000 0x0 0x1000>,
+				      <0x0 0xb8000000 0x0 0xc00000>;
+				reg-names = "QuadSPI", "QuadSPI-memory";
+				clocks = <&syscon_apmu CLK_QSPI_BUS>,
+					 <&syscon_apmu CLK_QSPI>;
+				clock-names = "qspi_en", "qspi";
+				resets = <&syscon_apmu RESET_QSPI>,
+					 <&syscon_apmu RESET_QSPI_BUS>;
+				interrupts = <117>;
+				status = "disabled";
+			};
+
 			sec_uart1: serial@f0612000 {
 				compatible = "spacemit,k1-uart",
 					     "intel,xscale-uart";