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[v2,02/10] configs: th1520_lpi4a: Add UART clock frequency

Message ID 20250513090503.46670-3-ziyao@disroot.org
State Accepted
Commit acf9384d8cc372fc71a5857363cfe10c240c497a
Delegated to: Andes
Headers show
Series Initial SPL support for T-Head TH1520 SoC | expand

Commit Message

Yao Zi May 13, 2025, 9:04 a.m. UTC
The BROM of TH1520 always initializes UART0's parent clock and
configures the baudrate to 115200. Describe the clock frequency to make
UART function correctly in SPL without introducing CCF.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 include/configs/th1520_lpi4a.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Leo Liang May 21, 2025, 8:22 a.m. UTC | #1
On Tue, May 13, 2025 at 09:04:55AM +0000, Yao Zi wrote:
> The BROM of TH1520 always initializes UART0's parent clock and
> configures the baudrate to 115200. Describe the clock frequency to make
> UART function correctly in SPL without introducing CCF.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  include/configs/th1520_lpi4a.h | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
index 87496a52c4c..7a9b70a3678 100644
--- a/include/configs/th1520_lpi4a.h
+++ b/include/configs/th1520_lpi4a.h
@@ -9,6 +9,7 @@ 
 
 #include <linux/sizes.h>
 
+#define CFG_SYS_NS16550_CLK		100000000
 #define CFG_SYS_SDRAM_BASE		0x00000000
 
 #define UART_BASE	0xffe7014000