diff mbox series

[v2,09/10] board: thead: licheepi4a: Enable SPL support

Message ID 20250513090503.46670-10-ziyao@disroot.org
State Accepted
Commit 38ed760bc90722207060ff16e370e4ea3f7f3db3
Delegated to: Andes
Headers show
Series Initial SPL support for T-Head TH1520 SoC | expand

Commit Message

Yao Zi May 13, 2025, 9:05 a.m. UTC 
Adjust Kconfig and defconfig and add SPL initialization code for
Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC
earlier. The board devicetree is changed to use TH1520 binman
configuration to generate bootable images.

Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/dts/th1520-lichee-pi-4a.dts |  1 +
 board/thead/th1520_lpi4a/Kconfig       |  5 +--
 board/thead/th1520_lpi4a/Makefile      |  1 +
 board/thead/th1520_lpi4a/spl.c         | 48 ++++++++++++++++++++++++++
 configs/th1520_lpi4a_defconfig         | 18 ++++++++++
 5 files changed, 71 insertions(+), 2 deletions(-)
 create mode 100644 board/thead/th1520_lpi4a/spl.c
diff mbox series

Patch

diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts b/arch/riscv/dts/th1520-lichee-pi-4a.dts
index a1248b2ee3a..49af88b7adf 100644
--- a/arch/riscv/dts/th1520-lichee-pi-4a.dts
+++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
@@ -4,6 +4,7 @@ 
  */
 
 #include "th1520-lichee-module-4a.dtsi"
+#include "thead-th1520-binman.dtsi"
 
 / {
 	model = "Sipeed Lichee Pi 4A";
diff --git a/board/thead/th1520_lpi4a/Kconfig b/board/thead/th1520_lpi4a/Kconfig
index 622246127c1..f139d5ff2bb 100644
--- a/board/thead/th1520_lpi4a/Kconfig
+++ b/board/thead/th1520_lpi4a/Kconfig
@@ -11,7 +11,7 @@  config SYS_VENDOR
 	default "thead"
 
 config SYS_CPU
-	default "generic"
+	default "th1520"
 
 config SYS_CONFIG_NAME
 	default "th1520_lpi4a"
@@ -22,7 +22,7 @@  config TEXT_BASE
 	default 0x01c00000 if RISCV_SMODE
 
 config SPL_TEXT_BASE
-	default 0x08000000
+	default 0xffe0000000
 
 config SPL_OPENSBI_LOAD_ADDR
 	default 0x80000000
@@ -30,6 +30,7 @@  config SPL_OPENSBI_LOAD_ADDR
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select ARCH_EARLY_INIT_R
+	select THEAD_TH1520
 	imply CPU
 	imply CPU_RISCV
 	imply RISCV_TIMER if RISCV_SMODE
diff --git a/board/thead/th1520_lpi4a/Makefile b/board/thead/th1520_lpi4a/Makefile
index 9671b3bbb0b..a7ddfc48d40 100644
--- a/board/thead/th1520_lpi4a/Makefile
+++ b/board/thead/th1520_lpi4a/Makefile
@@ -3,3 +3,4 @@ 
 # Copyright (c) 2023, Yixun Lan <dlan@gentoo.org>
 
 obj-y += board.o
+obj-$(CONFIG_XPL_BUILD) += spl.o
diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c
new file mode 100644
index 00000000000..25dfa387c36
--- /dev/null
+++ b/board/thead/th1520_lpi4a/spl.c
@@ -0,0 +1,48 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2025, Yao Zi <ziyao@disroot.org>
+ */
+
+#include <asm/io.h>
+#include <asm/spl.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/spl.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <hang.h>
+#include <spl.h>
+
+u32 spl_boot_device(void)
+{
+	/*
+	 * We don't bother to load proper U-Boot from an external device as
+	 * it fits in the integrated SRAM nicely.
+	 */
+	return BOOT_DEVICE_RAM;
+}
+
+void board_init_f(ulong dummy)
+{
+	int ret = spl_early_init();
+	struct udevice *dev;
+
+	if (ret)
+		panic("spl_early_init() failed %d\n", ret);
+
+	preloader_console_init();
+
+	/*
+	 * Manually bind CPU ahead of time to make sure in-core timers are
+	 * available in SPL.
+	 */
+	ret = uclass_get_device(UCLASS_CPU, 0, &dev);
+	if (ret)
+		panic("failed to bind CPU: %d\n", ret);
+
+	spl_dram_init();
+
+	icache_enable();
+	dcache_enable();
+
+	th1520_invalidate_pmp();
+}
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index d13c97463a8..b19dc009fde 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -90,3 +90,21 @@  CONFIG_ZLIB_UNCOMPRESS=y
 CONFIG_BZIP2=y
 CONFIG_ZSTD=y
 CONFIG_LIB_RATIONAL=y
+CONFIG_SPL=y
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_LOAD_FIT_ADDRESS=0xffe0040000
+CONFIG_SPL_HAVE_INIT_STACK=y
+CONFIG_SPL_STACK=0xffe0170000
+CONFIG_SPL_BSS_START_ADDR=0xffe0160000
+CONFIG_SPL_BSS_MAX_SIZE=0x10000
+CONFIG_SPL_MAX_SIZE=0x40000
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_SPL_THEAD_TH1520_DDR=y
+CONFIG_SPL_GPIO=y
+CONFIG_SPL_MMC_y
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
+CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x10000000
+CONFIG_SPL_SYS_MALLOC_SIZE=0x400000