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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070547; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E4ap557lfCQgYh5td6+jBPw28mHLUWYcaVFKktofZXI=; b=obkVuu+LhVw+akKpcjtYhdrYA5sAl1UP0JNUoiNotEradEA81nT3Jz0ptRMM1T5mguH6Rj 11QsyyJfpOYJUEPlprSJ6F2N1tLQhznhaAqV+uwGOBT5c5OsKI9W23DRmPaP5UZZsdhLDj qgtInk1s9AaMePg0sOZhQuceelS4gCuJCPhGYdrLndJ4Ap/DpUZlclwIuJ6gKnn/a386Te YEFFAoF3Rd5StFv2dBvxVBsz77PH0hRv+l+K3L+12P5mcO9fxC5GggH2QJRXm+MM5sz6Un HVyB6hZ/HKh9rBR0UK6+Ytbc335C80jNozNVRl0XkR4Qi/FLpC+cD0FounQHCA== To: u-boot@lists.denx.de Cc: Marek Vasut , Cheick Traore , Fabrice Gasnier , Gatien Chevallier , Lionel Debieve , Pascal Zimmermann , Patrice Chotard , Patrick Delaunay , Simon Glass , Sughosh Ganu , Tom Rini , u-boot@dh-electronics.com, uboot-stm32@st-md-mailman.stormreply.com Subject: [PATCH 08/10] ARM: dts: stm32: Add STM32MP13x SPL specific DT additions Date: Mon, 12 May 2025 19:21:35 +0200 Message-ID: <20250512172149.150214-9-marek.vasut@mailbox.org> In-Reply-To: <20250512172149.150214-1-marek.vasut@mailbox.org> References: <20250512172149.150214-1-marek.vasut@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: 3757f4041f8e38d1ded X-MBO-RS-META: buqzk47xma3oruqisbksijxkmktsexex X-Rspamd-Queue-Id: 4Zx5yY0V68z9tV1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Add DT additions required by U-Boot SPL to bring up the hardware. This includes binman node to generate STM32 Image v2.0 which can be booted by the BootROM, clock entries used by the SPL clock driver during clock tree initialization, and syscon-reboot node so U-Boot can reset the system without having to rely on PSCI call. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- arch/arm/dts/stm32mp13-u-boot.dtsi | 89 ++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi index 1fe6966781c..ad63d5027b2 100644 --- a/arch/arm/dts/stm32mp13-u-boot.dtsi +++ b/arch/arm/dts/stm32mp13-u-boot.dtsi @@ -17,6 +17,7 @@ pinctrl0 = &pinctrl; }; +#if defined(CONFIG_TFABOOT) firmware { optee { bootph-all; @@ -27,6 +28,86 @@ psci { bootph-some-ram; }; +#else + binman: binman { + multiple-images; + + spl-stm32 { + filename = "u-boot-spl.stm32"; + mkimage { + args = "-T stm32imagev2 -a 0x2ffe0000 -e 0x2ffe0000"; + u-boot-spl { + no-write-symbols; + }; + }; + }; + }; + + clocks { + bootph-all; + + clk_hse: ck_hse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_hsi: ck_hsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <64000000>; + }; + + clk_lse: ck_lse { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + + clk_lsi: ck_lsi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32000>; + }; + + clk_csi: ck_csi { + bootph-all; + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <4000000>; + }; + }; + + cpu0_opp_table: cpu0-opp-table { + compatible = "operating-points-v2"; + opp-shared; + bootph-pre-ram; + opp-650000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1200000>; + opp-supported-hw = <0x1>; + }; + opp-1000000000 { + bootph-pre-ram; + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1350000>; + opp-supported-hw = <0x2>; + }; + }; + + reboot { + bootph-all; + compatible = "syscon-reboot"; + regmap = <&rcc>; + offset = <0x114>; + mask = <0x1>; + }; +#endif soc { bootph-all; @@ -52,6 +133,14 @@ bootph-all; }; +#if !defined(CONFIG_TFABOOT) +&cpu0 { + nvmem-cells = <&part_number_otp>; + nvmem-cell-names = "part_number"; + operating-points-v2 = <&cpu0_opp_table>; +}; +#endif + &gpioa { bootph-all; };