diff mbox series

[06/10] ARM: dts: stm32: Add stm32mp13-ddr.dtsi template

Message ID 20250512172149.150214-7-marek.vasut@mailbox.org
State New
Delegated to: Patrice Chotard
Headers show
Series ARM: stm32: Add STM32MP13xx SPL and OpTee-OS start support | expand

Commit Message

Marek Vasut May 12, 2025, 5:21 p.m. UTC 
Factor out common parts of STM32MP15xx DRAM controller configuration DT
description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
describes STM32MP13xx DRAM controller configuration in DT.

Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
---
Cc: Cheick Traore <cheick.traore@foss.st.com>
Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Cc: Gatien Chevallier <gatien.chevallier@foss.st.com>
Cc: Lionel Debieve <lionel.debieve@foss.st.com>
Cc: Pascal Zimmermann <pzimmermann@dh-electronics.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: u-boot@dh-electronics.com
Cc: u-boot@lists.denx.de
Cc: uboot-stm32@st-md-mailman.stormreply.com
---
 arch/arm/dts/stm32mp1-ddr.dtsi  | 187 ++++++++++++++++++++++++++++++++
 arch/arm/dts/stm32mp13-ddr.dtsi |  49 +++++++++
 arch/arm/dts/stm32mp15-ddr.dtsi | 170 +----------------------------
 3 files changed, 237 insertions(+), 169 deletions(-)
 create mode 100644 arch/arm/dts/stm32mp1-ddr.dtsi
 create mode 100644 arch/arm/dts/stm32mp13-ddr.dtsi

Comments

Patrice CHOTARD May 28, 2025, 6:34 a.m. UTC | #1 
On 5/12/25 19:21, Marek Vasut wrote:
> Factor out common parts of STM32MP15xx DRAM controller configuration DT
> description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
> describes STM32MP13xx DRAM controller configuration in DT.
> 
> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
> ---
> Cc: Cheick Traore <cheick.traore@foss.st.com>
> Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
> Cc: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Cc: Lionel Debieve <lionel.debieve@foss.st.com>
> Cc: Pascal Zimmermann <pzimmermann@dh-electronics.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: u-boot@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-stm32@st-md-mailman.stormreply.com
> ---
>  arch/arm/dts/stm32mp1-ddr.dtsi  | 187 ++++++++++++++++++++++++++++++++
>  arch/arm/dts/stm32mp13-ddr.dtsi |  49 +++++++++
>  arch/arm/dts/stm32mp15-ddr.dtsi | 170 +----------------------------
>  3 files changed, 237 insertions(+), 169 deletions(-)
>  create mode 100644 arch/arm/dts/stm32mp1-ddr.dtsi
>  create mode 100644 arch/arm/dts/stm32mp13-ddr.dtsi
> 
> diff --git a/arch/arm/dts/stm32mp1-ddr.dtsi b/arch/arm/dts/stm32mp1-ddr.dtsi
> new file mode 100644
> index 00000000000..da9f9fac4b8
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp1-ddr.dtsi
> @@ -0,0 +1,187 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright : STMicroelectronics 2018
> + */
> +#include <linux/stringify.h>
> +
> +#ifdef CONFIG_SPL
> +&ddr {
> +	config-DDR_MEM_COMPATIBLE {
> +		bootph-all;
> +
> +		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
> +
> +		st,mem-name = DDR_MEM_NAME;
> +		st,mem-speed = <DDR_MEM_SPEED>;
> +		st,mem-size = <DDR_MEM_SIZE>;
> +
> +		st,ctl-reg = <
> +			DDR_MSTR
> +			DDR_MRCTRL0
> +			DDR_MRCTRL1
> +			DDR_DERATEEN
> +			DDR_DERATEINT
> +			DDR_PWRCTL
> +			DDR_PWRTMG
> +			DDR_HWLPCTL
> +			DDR_RFSHCTL0
> +			DDR_RFSHCTL3
> +			DDR_CRCPARCTL0
> +			DDR_ZQCTL0
> +			DDR_DFITMG0
> +			DDR_DFITMG1
> +			DDR_DFILPCFG0
> +			DDR_DFIUPD0
> +			DDR_DFIUPD1
> +			DDR_DFIUPD2
> +			DDR_DFIPHYMSTR
> +			DDR_ODTMAP
> +			DDR_DBG0
> +			DDR_DBG1
> +			DDR_DBGCMD
> +			DDR_POISONCFG
> +			DDR_PCCFG
> +		>;
> +
> +		st,ctl-timing = <
> +			DDR_RFSHTMG
> +			DDR_DRAMTMG0
> +			DDR_DRAMTMG1
> +			DDR_DRAMTMG2
> +			DDR_DRAMTMG3
> +			DDR_DRAMTMG4
> +			DDR_DRAMTMG5
> +			DDR_DRAMTMG6
> +			DDR_DRAMTMG7
> +			DDR_DRAMTMG8
> +			DDR_DRAMTMG14
> +			DDR_ODTCFG
> +		>;
> +
> +		st,ctl-map = <
> +			DDR_ADDRMAP1
> +			DDR_ADDRMAP2
> +			DDR_ADDRMAP3
> +			DDR_ADDRMAP4
> +			DDR_ADDRMAP5
> +			DDR_ADDRMAP6
> +			DDR_ADDRMAP9
> +			DDR_ADDRMAP10
> +			DDR_ADDRMAP11
> +		>;
> +
> +
> +		/*
> +		 * Both st,ctl-perf and st,phy-reg differ
> +		 * between STM32MP13xx and STM32MP15xx due
> +		 * to 16bit and 32bit DRAM bus respectively
> +		 * on these SoCs.
> +		 */
> +
> +		st,phy-timing = <
> +			DDR_PTR0
> +			DDR_PTR1
> +			DDR_PTR2
> +			DDR_DTPR0
> +			DDR_DTPR1
> +			DDR_DTPR2
> +			DDR_MR0
> +			DDR_MR1
> +			DDR_MR2
> +			DDR_MR3
> +		>;
> +
> +		status = "okay";
> +	};
> +};
> +#endif
> +
> +#undef DDR_MEM_COMPATIBLE
> +#undef DDR_MEM_NAME
> +#undef DDR_MEM_SPEED
> +#undef DDR_MEM_SIZE
> +
> +#undef DDR_MSTR
> +#undef DDR_MRCTRL0
> +#undef DDR_MRCTRL1
> +#undef DDR_DERATEEN
> +#undef DDR_DERATEINT
> +#undef DDR_PWRCTL
> +#undef DDR_PWRTMG
> +#undef DDR_HWLPCTL
> +#undef DDR_RFSHCTL0
> +#undef DDR_RFSHCTL3
> +#undef DDR_RFSHTMG
> +#undef DDR_CRCPARCTL0
> +#undef DDR_DRAMTMG0
> +#undef DDR_DRAMTMG1
> +#undef DDR_DRAMTMG2
> +#undef DDR_DRAMTMG3
> +#undef DDR_DRAMTMG4
> +#undef DDR_DRAMTMG5
> +#undef DDR_DRAMTMG6
> +#undef DDR_DRAMTMG7
> +#undef DDR_DRAMTMG8
> +#undef DDR_DRAMTMG14
> +#undef DDR_ZQCTL0
> +#undef DDR_DFITMG0
> +#undef DDR_DFITMG1
> +#undef DDR_DFILPCFG0
> +#undef DDR_DFIUPD0
> +#undef DDR_DFIUPD1
> +#undef DDR_DFIUPD2
> +#undef DDR_DFIPHYMSTR
> +#undef DDR_ADDRMAP1
> +#undef DDR_ADDRMAP2
> +#undef DDR_ADDRMAP3
> +#undef DDR_ADDRMAP4
> +#undef DDR_ADDRMAP5
> +#undef DDR_ADDRMAP6
> +#undef DDR_ADDRMAP9
> +#undef DDR_ADDRMAP10
> +#undef DDR_ADDRMAP11
> +#undef DDR_ODTCFG
> +#undef DDR_ODTMAP
> +#undef DDR_SCHED
> +#undef DDR_SCHED1
> +#undef DDR_PERFHPR1
> +#undef DDR_PERFLPR1
> +#undef DDR_PERFWR1
> +#undef DDR_DBG0
> +#undef DDR_DBG1
> +#undef DDR_DBGCMD
> +#undef DDR_POISONCFG
> +#undef DDR_PCCFG
> +#undef DDR_PCFGR_0
> +#undef DDR_PCFGW_0
> +#undef DDR_PCFGQOS0_0
> +#undef DDR_PCFGQOS1_0
> +#undef DDR_PCFGWQOS0_0
> +#undef DDR_PCFGWQOS1_0
> +#undef DDR_PCFGR_1
> +#undef DDR_PCFGW_1
> +#undef DDR_PCFGQOS0_1
> +#undef DDR_PCFGQOS1_1
> +#undef DDR_PCFGWQOS0_1
> +#undef DDR_PCFGWQOS1_1
> +#undef DDR_PGCR
> +#undef DDR_PTR0
> +#undef DDR_PTR1
> +#undef DDR_PTR2
> +#undef DDR_ACIOCR
> +#undef DDR_DXCCR
> +#undef DDR_DSGCR
> +#undef DDR_DCR
> +#undef DDR_DTPR0
> +#undef DDR_DTPR1
> +#undef DDR_DTPR2
> +#undef DDR_MR0
> +#undef DDR_MR1
> +#undef DDR_MR2
> +#undef DDR_MR3
> +#undef DDR_ODTCR
> +#undef DDR_ZQ0CR1
> +#undef DDR_DX0GCR
> +#undef DDR_DX1GCR
> +#undef DDR_DX2GCR
> +#undef DDR_DX3GCR
> diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi
> new file mode 100644
> index 00000000000..30d8c5014e0
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp13-ddr.dtsi
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
> +/*
> + * Copyright : STMicroelectronics 2018
> + */
> +#ifdef CONFIG_SPL
> +&ddr {
> +	clocks = <&rcc AXIDCG>,
> +		 <&rcc DDRC1>,
> +		 <&rcc DDRPHYC>,
> +		 <&rcc DDRCAPB>,
> +		 <&rcc DDRPHYCAPB>;
> +
> +	clock-names = "axidcg",
> +		      "ddrc1",
> +		      "ddrphyc",
> +		      "ddrcapb",
> +		      "ddrphycapb";
> +
> +	config-DDR_MEM_COMPATIBLE {
> +		st,ctl-perf = <
> +			DDR_SCHED
> +			DDR_SCHED1
> +			DDR_PERFHPR1
> +			DDR_PERFLPR1
> +			DDR_PERFWR1
> +			DDR_PCFGR_0
> +			DDR_PCFGW_0
> +			DDR_PCFGQOS0_0
> +			DDR_PCFGQOS1_0
> +			DDR_PCFGWQOS0_0
> +			DDR_PCFGWQOS1_0
> +		>;
> +
> +		st,phy-reg = <
> +			DDR_PGCR
> +			DDR_ACIOCR
> +			DDR_DXCCR
> +			DDR_DSGCR
> +			DDR_DCR
> +			DDR_ODTCR
> +			DDR_ZQ0CR1
> +			DDR_DX0GCR
> +			DDR_DX1GCR
> +		>;
> +	};
> +};
> +#endif
> +
> +#include "stm32mp1-ddr.dtsi"
> diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
> index 48b0828828f..f18fdaeab68 100644
> --- a/arch/arm/dts/stm32mp15-ddr.dtsi
> +++ b/arch/arm/dts/stm32mp15-ddr.dtsi
> @@ -2,8 +2,6 @@
>  /*
>   * Copyright : STMicroelectronics 2018
>   */
> -#include <linux/stringify.h>
> -
>  #ifdef CONFIG_SPL
>  &ddr {
>  	clocks = <&rcc AXIDCG>,
> @@ -21,69 +19,6 @@
>  		      "ddrphycapb";
>  
>  	config-DDR_MEM_COMPATIBLE {
> -		bootph-all;
> -
> -		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
> -
> -		st,mem-name = DDR_MEM_NAME;
> -		st,mem-speed = <DDR_MEM_SPEED>;
> -		st,mem-size = <DDR_MEM_SIZE>;
> -
> -		st,ctl-reg = <
> -			DDR_MSTR
> -			DDR_MRCTRL0
> -			DDR_MRCTRL1
> -			DDR_DERATEEN
> -			DDR_DERATEINT
> -			DDR_PWRCTL
> -			DDR_PWRTMG
> -			DDR_HWLPCTL
> -			DDR_RFSHCTL0
> -			DDR_RFSHCTL3
> -			DDR_CRCPARCTL0
> -			DDR_ZQCTL0
> -			DDR_DFITMG0
> -			DDR_DFITMG1
> -			DDR_DFILPCFG0
> -			DDR_DFIUPD0
> -			DDR_DFIUPD1
> -			DDR_DFIUPD2
> -			DDR_DFIPHYMSTR
> -			DDR_ODTMAP
> -			DDR_DBG0
> -			DDR_DBG1
> -			DDR_DBGCMD
> -			DDR_POISONCFG
> -			DDR_PCCFG
> -		>;
> -
> -		st,ctl-timing = <
> -			DDR_RFSHTMG
> -			DDR_DRAMTMG0
> -			DDR_DRAMTMG1
> -			DDR_DRAMTMG2
> -			DDR_DRAMTMG3
> -			DDR_DRAMTMG4
> -			DDR_DRAMTMG5
> -			DDR_DRAMTMG6
> -			DDR_DRAMTMG7
> -			DDR_DRAMTMG8
> -			DDR_DRAMTMG14
> -			DDR_ODTCFG
> -		>;
> -
> -		st,ctl-map = <
> -			DDR_ADDRMAP1
> -			DDR_ADDRMAP2
> -			DDR_ADDRMAP3
> -			DDR_ADDRMAP4
> -			DDR_ADDRMAP5
> -			DDR_ADDRMAP6
> -			DDR_ADDRMAP9
> -			DDR_ADDRMAP10
> -			DDR_ADDRMAP11
> -		>;
> -
>  		st,ctl-perf = <
>  			DDR_SCHED
>  			DDR_SCHED1
> @@ -117,111 +52,8 @@
>  			DDR_DX2GCR
>  			DDR_DX3GCR
>  		>;
> -
> -		st,phy-timing = <
> -			DDR_PTR0
> -			DDR_PTR1
> -			DDR_PTR2
> -			DDR_DTPR0
> -			DDR_DTPR1
> -			DDR_DTPR2
> -			DDR_MR0
> -			DDR_MR1
> -			DDR_MR2
> -			DDR_MR3
> -		>;
> -
> -		status = "okay";
>  	};
>  };
>  #endif
>  
> -#undef DDR_MEM_COMPATIBLE
> -#undef DDR_MEM_NAME
> -#undef DDR_MEM_SPEED
> -#undef DDR_MEM_SIZE
> -
> -#undef DDR_MSTR
> -#undef DDR_MRCTRL0
> -#undef DDR_MRCTRL1
> -#undef DDR_DERATEEN
> -#undef DDR_DERATEINT
> -#undef DDR_PWRCTL
> -#undef DDR_PWRTMG
> -#undef DDR_HWLPCTL
> -#undef DDR_RFSHCTL0
> -#undef DDR_RFSHCTL3
> -#undef DDR_RFSHTMG
> -#undef DDR_CRCPARCTL0
> -#undef DDR_DRAMTMG0
> -#undef DDR_DRAMTMG1
> -#undef DDR_DRAMTMG2
> -#undef DDR_DRAMTMG3
> -#undef DDR_DRAMTMG4
> -#undef DDR_DRAMTMG5
> -#undef DDR_DRAMTMG6
> -#undef DDR_DRAMTMG7
> -#undef DDR_DRAMTMG8
> -#undef DDR_DRAMTMG14
> -#undef DDR_ZQCTL0
> -#undef DDR_DFITMG0
> -#undef DDR_DFITMG1
> -#undef DDR_DFILPCFG0
> -#undef DDR_DFIUPD0
> -#undef DDR_DFIUPD1
> -#undef DDR_DFIUPD2
> -#undef DDR_DFIPHYMSTR
> -#undef DDR_ADDRMAP1
> -#undef DDR_ADDRMAP2
> -#undef DDR_ADDRMAP3
> -#undef DDR_ADDRMAP4
> -#undef DDR_ADDRMAP5
> -#undef DDR_ADDRMAP6
> -#undef DDR_ADDRMAP9
> -#undef DDR_ADDRMAP10
> -#undef DDR_ADDRMAP11
> -#undef DDR_ODTCFG
> -#undef DDR_ODTMAP
> -#undef DDR_SCHED
> -#undef DDR_SCHED1
> -#undef DDR_PERFHPR1
> -#undef DDR_PERFLPR1
> -#undef DDR_PERFWR1
> -#undef DDR_DBG0
> -#undef DDR_DBG1
> -#undef DDR_DBGCMD
> -#undef DDR_POISONCFG
> -#undef DDR_PCCFG
> -#undef DDR_PCFGR_0
> -#undef DDR_PCFGW_0
> -#undef DDR_PCFGQOS0_0
> -#undef DDR_PCFGQOS1_0
> -#undef DDR_PCFGWQOS0_0
> -#undef DDR_PCFGWQOS1_0
> -#undef DDR_PCFGR_1
> -#undef DDR_PCFGW_1
> -#undef DDR_PCFGQOS0_1
> -#undef DDR_PCFGQOS1_1
> -#undef DDR_PCFGWQOS0_1
> -#undef DDR_PCFGWQOS1_1
> -#undef DDR_PGCR
> -#undef DDR_PTR0
> -#undef DDR_PTR1
> -#undef DDR_PTR2
> -#undef DDR_ACIOCR
> -#undef DDR_DXCCR
> -#undef DDR_DSGCR
> -#undef DDR_DCR
> -#undef DDR_DTPR0
> -#undef DDR_DTPR1
> -#undef DDR_DTPR2
> -#undef DDR_MR0
> -#undef DDR_MR1
> -#undef DDR_MR2
> -#undef DDR_MR3
> -#undef DDR_ODTCR
> -#undef DDR_ZQ0CR1
> -#undef DDR_DX0GCR
> -#undef DDR_DX1GCR
> -#undef DDR_DX2GCR
> -#undef DDR_DX3GCR
> +#include "stm32mp1-ddr.dtsi"

Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

Thanks
Patrice
Patrick DELAUNAY June 3, 2025, 2:22 p.m. UTC | #2 
Hi,

On 5/12/25 19:21, Marek Vasut wrote:
> Factor out common parts of STM32MP15xx DRAM controller configuration DT
> description into stm32mp1-ddr.dtsi and introduce stm32mp13-ddr.dtsi which
> describes STM32MP13xx DRAM controller configuration in DT.
>
> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
> ---
> Cc: Cheick Traore <cheick.traore@foss.st.com>
> Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
> Cc: Gatien Chevallier <gatien.chevallier@foss.st.com>
> Cc: Lionel Debieve <lionel.debieve@foss.st.com>
> Cc: Pascal Zimmermann <pzimmermann@dh-electronics.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: Simon Glass <sjg@chromium.org>
> Cc: Sughosh Ganu <sughosh.ganu@linaro.org>
> Cc: Tom Rini <trini@konsulko.com>
> Cc: u-boot@dh-electronics.com
> Cc: u-boot@lists.denx.de
> Cc: uboot-stm32@st-md-mailman.stormreply.com
> ---
>   arch/arm/dts/stm32mp1-ddr.dtsi  | 187 ++++++++++++++++++++++++++++++++
>   arch/arm/dts/stm32mp13-ddr.dtsi |  49 +++++++++
>   arch/arm/dts/stm32mp15-ddr.dtsi | 170 +----------------------------
>   3 files changed, 237 insertions(+), 169 deletions(-)
>   create mode 100644 arch/arm/dts/stm32mp1-ddr.dtsi
>   create mode 100644 arch/arm/dts/stm32mp13-ddr.dtsi
>
....
> diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi
> new file mode 100644
> index 00000000000..30d8c5014e0
> --- /dev/null
> +++ b/arch/arm/dts/stm32mp13-ddr.dtsi
> @@ -0,0 +1,49 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause


For new STM32MP file avoids to use the Deprecated License Identifiers 
(GPL-2.0+ / GPL-2.0)

reference=

+https://spdx.dev/learn/handling-license-info/

+ https://spdx.org/licenses/


=>

SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause


> +/*
> + * Copyright : STMicroelectronics 2018


This copyright, with year 2018 is strange this file is copied for TF-A 
file, I think = ./fdts/stm32mp13-ddr.dtsi


Copyright (C) 2022, STMicroelectronics - All Rights Reserved


> + */
> +#ifdef CONFIG_SPL
> +&ddr {
> +	clocks = <&rcc AXIDCG>,
> +		 <&rcc DDRC1>,
> +		 <&rcc DDRPHYC>,
> +		 <&rcc DDRCAPB>,
> +		 <&rcc DDRPHYCAPB>;
> +
> +	clock-names = "axidcg",
> +		      "ddrc1",
> +		      "ddrphyc",
> +		      "ddrcapb",
> +		      "ddrphycapb";
> +
> +	config-DDR_MEM_COMPATIBLE {
> +		st,ctl-perf = <
> +			DDR_SCHED
> +			DDR_SCHED1
> +			DDR_PERFHPR1
> +			DDR_PERFLPR1
> +			DDR_PERFWR1
> +			DDR_PCFGR_0
> +			DDR_PCFGW_0
> +			DDR_PCFGQOS0_0
> +			DDR_PCFGQOS1_0
> +			DDR_PCFGWQOS0_0
> +			DDR_PCFGWQOS1_0
> +		>;
> +
> +		st,phy-reg = <
> +			DDR_PGCR
> +			DDR_ACIOCR
> +			DDR_DXCCR
> +			DDR_DSGCR
> +			DDR_DCR
> +			DDR_ODTCR
> +			DDR_ZQ0CR1
> +			DDR_DX0GCR
> +			DDR_DX1GCR
> +		>;
> +	};
> +};
> +#endif
> +
> +#include "stm32mp1-ddr.dtsi"

...

Witth the minor updates

Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>

Thanks
Patrick
diff mbox series

Patch

diff --git a/arch/arm/dts/stm32mp1-ddr.dtsi b/arch/arm/dts/stm32mp1-ddr.dtsi
new file mode 100644
index 00000000000..da9f9fac4b8
--- /dev/null
+++ b/arch/arm/dts/stm32mp1-ddr.dtsi
@@ -0,0 +1,187 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2018
+ */
+#include <linux/stringify.h>
+
+#ifdef CONFIG_SPL
+&ddr {
+	config-DDR_MEM_COMPATIBLE {
+		bootph-all;
+
+		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
+
+		st,mem-name = DDR_MEM_NAME;
+		st,mem-speed = <DDR_MEM_SPEED>;
+		st,mem-size = <DDR_MEM_SIZE>;
+
+		st,ctl-reg = <
+			DDR_MSTR
+			DDR_MRCTRL0
+			DDR_MRCTRL1
+			DDR_DERATEEN
+			DDR_DERATEINT
+			DDR_PWRCTL
+			DDR_PWRTMG
+			DDR_HWLPCTL
+			DDR_RFSHCTL0
+			DDR_RFSHCTL3
+			DDR_CRCPARCTL0
+			DDR_ZQCTL0
+			DDR_DFITMG0
+			DDR_DFITMG1
+			DDR_DFILPCFG0
+			DDR_DFIUPD0
+			DDR_DFIUPD1
+			DDR_DFIUPD2
+			DDR_DFIPHYMSTR
+			DDR_ODTMAP
+			DDR_DBG0
+			DDR_DBG1
+			DDR_DBGCMD
+			DDR_POISONCFG
+			DDR_PCCFG
+		>;
+
+		st,ctl-timing = <
+			DDR_RFSHTMG
+			DDR_DRAMTMG0
+			DDR_DRAMTMG1
+			DDR_DRAMTMG2
+			DDR_DRAMTMG3
+			DDR_DRAMTMG4
+			DDR_DRAMTMG5
+			DDR_DRAMTMG6
+			DDR_DRAMTMG7
+			DDR_DRAMTMG8
+			DDR_DRAMTMG14
+			DDR_ODTCFG
+		>;
+
+		st,ctl-map = <
+			DDR_ADDRMAP1
+			DDR_ADDRMAP2
+			DDR_ADDRMAP3
+			DDR_ADDRMAP4
+			DDR_ADDRMAP5
+			DDR_ADDRMAP6
+			DDR_ADDRMAP9
+			DDR_ADDRMAP10
+			DDR_ADDRMAP11
+		>;
+
+
+		/*
+		 * Both st,ctl-perf and st,phy-reg differ
+		 * between STM32MP13xx and STM32MP15xx due
+		 * to 16bit and 32bit DRAM bus respectively
+		 * on these SoCs.
+		 */
+
+		st,phy-timing = <
+			DDR_PTR0
+			DDR_PTR1
+			DDR_PTR2
+			DDR_DTPR0
+			DDR_DTPR1
+			DDR_DTPR2
+			DDR_MR0
+			DDR_MR1
+			DDR_MR2
+			DDR_MR3
+		>;
+
+		status = "okay";
+	};
+};
+#endif
+
+#undef DDR_MEM_COMPATIBLE
+#undef DDR_MEM_NAME
+#undef DDR_MEM_SPEED
+#undef DDR_MEM_SIZE
+
+#undef DDR_MSTR
+#undef DDR_MRCTRL0
+#undef DDR_MRCTRL1
+#undef DDR_DERATEEN
+#undef DDR_DERATEINT
+#undef DDR_PWRCTL
+#undef DDR_PWRTMG
+#undef DDR_HWLPCTL
+#undef DDR_RFSHCTL0
+#undef DDR_RFSHCTL3
+#undef DDR_RFSHTMG
+#undef DDR_CRCPARCTL0
+#undef DDR_DRAMTMG0
+#undef DDR_DRAMTMG1
+#undef DDR_DRAMTMG2
+#undef DDR_DRAMTMG3
+#undef DDR_DRAMTMG4
+#undef DDR_DRAMTMG5
+#undef DDR_DRAMTMG6
+#undef DDR_DRAMTMG7
+#undef DDR_DRAMTMG8
+#undef DDR_DRAMTMG14
+#undef DDR_ZQCTL0
+#undef DDR_DFITMG0
+#undef DDR_DFITMG1
+#undef DDR_DFILPCFG0
+#undef DDR_DFIUPD0
+#undef DDR_DFIUPD1
+#undef DDR_DFIUPD2
+#undef DDR_DFIPHYMSTR
+#undef DDR_ADDRMAP1
+#undef DDR_ADDRMAP2
+#undef DDR_ADDRMAP3
+#undef DDR_ADDRMAP4
+#undef DDR_ADDRMAP5
+#undef DDR_ADDRMAP6
+#undef DDR_ADDRMAP9
+#undef DDR_ADDRMAP10
+#undef DDR_ADDRMAP11
+#undef DDR_ODTCFG
+#undef DDR_ODTMAP
+#undef DDR_SCHED
+#undef DDR_SCHED1
+#undef DDR_PERFHPR1
+#undef DDR_PERFLPR1
+#undef DDR_PERFWR1
+#undef DDR_DBG0
+#undef DDR_DBG1
+#undef DDR_DBGCMD
+#undef DDR_POISONCFG
+#undef DDR_PCCFG
+#undef DDR_PCFGR_0
+#undef DDR_PCFGW_0
+#undef DDR_PCFGQOS0_0
+#undef DDR_PCFGQOS1_0
+#undef DDR_PCFGWQOS0_0
+#undef DDR_PCFGWQOS1_0
+#undef DDR_PCFGR_1
+#undef DDR_PCFGW_1
+#undef DDR_PCFGQOS0_1
+#undef DDR_PCFGQOS1_1
+#undef DDR_PCFGWQOS0_1
+#undef DDR_PCFGWQOS1_1
+#undef DDR_PGCR
+#undef DDR_PTR0
+#undef DDR_PTR1
+#undef DDR_PTR2
+#undef DDR_ACIOCR
+#undef DDR_DXCCR
+#undef DDR_DSGCR
+#undef DDR_DCR
+#undef DDR_DTPR0
+#undef DDR_DTPR1
+#undef DDR_DTPR2
+#undef DDR_MR0
+#undef DDR_MR1
+#undef DDR_MR2
+#undef DDR_MR3
+#undef DDR_ODTCR
+#undef DDR_ZQ0CR1
+#undef DDR_DX0GCR
+#undef DDR_DX1GCR
+#undef DDR_DX2GCR
+#undef DDR_DX3GCR
diff --git a/arch/arm/dts/stm32mp13-ddr.dtsi b/arch/arm/dts/stm32mp13-ddr.dtsi
new file mode 100644
index 00000000000..30d8c5014e0
--- /dev/null
+++ b/arch/arm/dts/stm32mp13-ddr.dtsi
@@ -0,0 +1,49 @@ 
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright : STMicroelectronics 2018
+ */
+#ifdef CONFIG_SPL
+&ddr {
+	clocks = <&rcc AXIDCG>,
+		 <&rcc DDRC1>,
+		 <&rcc DDRPHYC>,
+		 <&rcc DDRCAPB>,
+		 <&rcc DDRPHYCAPB>;
+
+	clock-names = "axidcg",
+		      "ddrc1",
+		      "ddrphyc",
+		      "ddrcapb",
+		      "ddrphycapb";
+
+	config-DDR_MEM_COMPATIBLE {
+		st,ctl-perf = <
+			DDR_SCHED
+			DDR_SCHED1
+			DDR_PERFHPR1
+			DDR_PERFLPR1
+			DDR_PERFWR1
+			DDR_PCFGR_0
+			DDR_PCFGW_0
+			DDR_PCFGQOS0_0
+			DDR_PCFGQOS1_0
+			DDR_PCFGWQOS0_0
+			DDR_PCFGWQOS1_0
+		>;
+
+		st,phy-reg = <
+			DDR_PGCR
+			DDR_ACIOCR
+			DDR_DXCCR
+			DDR_DSGCR
+			DDR_DCR
+			DDR_ODTCR
+			DDR_ZQ0CR1
+			DDR_DX0GCR
+			DDR_DX1GCR
+		>;
+	};
+};
+#endif
+
+#include "stm32mp1-ddr.dtsi"
diff --git a/arch/arm/dts/stm32mp15-ddr.dtsi b/arch/arm/dts/stm32mp15-ddr.dtsi
index 48b0828828f..f18fdaeab68 100644
--- a/arch/arm/dts/stm32mp15-ddr.dtsi
+++ b/arch/arm/dts/stm32mp15-ddr.dtsi
@@ -2,8 +2,6 @@ 
 /*
  * Copyright : STMicroelectronics 2018
  */
-#include <linux/stringify.h>
-
 #ifdef CONFIG_SPL
 &ddr {
 	clocks = <&rcc AXIDCG>,
@@ -21,69 +19,6 @@ 
 		      "ddrphycapb";
 
 	config-DDR_MEM_COMPATIBLE {
-		bootph-all;
-
-		compatible = __stringify(st,DDR_MEM_COMPATIBLE);
-
-		st,mem-name = DDR_MEM_NAME;
-		st,mem-speed = <DDR_MEM_SPEED>;
-		st,mem-size = <DDR_MEM_SIZE>;
-
-		st,ctl-reg = <
-			DDR_MSTR
-			DDR_MRCTRL0
-			DDR_MRCTRL1
-			DDR_DERATEEN
-			DDR_DERATEINT
-			DDR_PWRCTL
-			DDR_PWRTMG
-			DDR_HWLPCTL
-			DDR_RFSHCTL0
-			DDR_RFSHCTL3
-			DDR_CRCPARCTL0
-			DDR_ZQCTL0
-			DDR_DFITMG0
-			DDR_DFITMG1
-			DDR_DFILPCFG0
-			DDR_DFIUPD0
-			DDR_DFIUPD1
-			DDR_DFIUPD2
-			DDR_DFIPHYMSTR
-			DDR_ODTMAP
-			DDR_DBG0
-			DDR_DBG1
-			DDR_DBGCMD
-			DDR_POISONCFG
-			DDR_PCCFG
-		>;
-
-		st,ctl-timing = <
-			DDR_RFSHTMG
-			DDR_DRAMTMG0
-			DDR_DRAMTMG1
-			DDR_DRAMTMG2
-			DDR_DRAMTMG3
-			DDR_DRAMTMG4
-			DDR_DRAMTMG5
-			DDR_DRAMTMG6
-			DDR_DRAMTMG7
-			DDR_DRAMTMG8
-			DDR_DRAMTMG14
-			DDR_ODTCFG
-		>;
-
-		st,ctl-map = <
-			DDR_ADDRMAP1
-			DDR_ADDRMAP2
-			DDR_ADDRMAP3
-			DDR_ADDRMAP4
-			DDR_ADDRMAP5
-			DDR_ADDRMAP6
-			DDR_ADDRMAP9
-			DDR_ADDRMAP10
-			DDR_ADDRMAP11
-		>;
-
 		st,ctl-perf = <
 			DDR_SCHED
 			DDR_SCHED1
@@ -117,111 +52,8 @@ 
 			DDR_DX2GCR
 			DDR_DX3GCR
 		>;
-
-		st,phy-timing = <
-			DDR_PTR0
-			DDR_PTR1
-			DDR_PTR2
-			DDR_DTPR0
-			DDR_DTPR1
-			DDR_DTPR2
-			DDR_MR0
-			DDR_MR1
-			DDR_MR2
-			DDR_MR3
-		>;
-
-		status = "okay";
 	};
 };
 #endif
 
-#undef DDR_MEM_COMPATIBLE
-#undef DDR_MEM_NAME
-#undef DDR_MEM_SPEED
-#undef DDR_MEM_SIZE
-
-#undef DDR_MSTR
-#undef DDR_MRCTRL0
-#undef DDR_MRCTRL1
-#undef DDR_DERATEEN
-#undef DDR_DERATEINT
-#undef DDR_PWRCTL
-#undef DDR_PWRTMG
-#undef DDR_HWLPCTL
-#undef DDR_RFSHCTL0
-#undef DDR_RFSHCTL3
-#undef DDR_RFSHTMG
-#undef DDR_CRCPARCTL0
-#undef DDR_DRAMTMG0
-#undef DDR_DRAMTMG1
-#undef DDR_DRAMTMG2
-#undef DDR_DRAMTMG3
-#undef DDR_DRAMTMG4
-#undef DDR_DRAMTMG5
-#undef DDR_DRAMTMG6
-#undef DDR_DRAMTMG7
-#undef DDR_DRAMTMG8
-#undef DDR_DRAMTMG14
-#undef DDR_ZQCTL0
-#undef DDR_DFITMG0
-#undef DDR_DFITMG1
-#undef DDR_DFILPCFG0
-#undef DDR_DFIUPD0
-#undef DDR_DFIUPD1
-#undef DDR_DFIUPD2
-#undef DDR_DFIPHYMSTR
-#undef DDR_ADDRMAP1
-#undef DDR_ADDRMAP2
-#undef DDR_ADDRMAP3
-#undef DDR_ADDRMAP4
-#undef DDR_ADDRMAP5
-#undef DDR_ADDRMAP6
-#undef DDR_ADDRMAP9
-#undef DDR_ADDRMAP10
-#undef DDR_ADDRMAP11
-#undef DDR_ODTCFG
-#undef DDR_ODTMAP
-#undef DDR_SCHED
-#undef DDR_SCHED1
-#undef DDR_PERFHPR1
-#undef DDR_PERFLPR1
-#undef DDR_PERFWR1
-#undef DDR_DBG0
-#undef DDR_DBG1
-#undef DDR_DBGCMD
-#undef DDR_POISONCFG
-#undef DDR_PCCFG
-#undef DDR_PCFGR_0
-#undef DDR_PCFGW_0
-#undef DDR_PCFGQOS0_0
-#undef DDR_PCFGQOS1_0
-#undef DDR_PCFGWQOS0_0
-#undef DDR_PCFGWQOS1_0
-#undef DDR_PCFGR_1
-#undef DDR_PCFGW_1
-#undef DDR_PCFGQOS0_1
-#undef DDR_PCFGQOS1_1
-#undef DDR_PCFGWQOS0_1
-#undef DDR_PCFGWQOS1_1
-#undef DDR_PGCR
-#undef DDR_PTR0
-#undef DDR_PTR1
-#undef DDR_PTR2
-#undef DDR_ACIOCR
-#undef DDR_DXCCR
-#undef DDR_DSGCR
-#undef DDR_DCR
-#undef DDR_DTPR0
-#undef DDR_DTPR1
-#undef DDR_DTPR2
-#undef DDR_MR0
-#undef DDR_MR1
-#undef DDR_MR2
-#undef DDR_MR3
-#undef DDR_ODTCR
-#undef DDR_ZQ0CR1
-#undef DDR_DX0GCR
-#undef DDR_DX1GCR
-#undef DDR_DX2GCR
-#undef DDR_DX3GCR
+#include "stm32mp1-ddr.dtsi"