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a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1747070540; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=wlQeXKprmnnpWWXsbmVTnZIw+/Hde1MGFbCAtnDBLh8=; b=QOEsUC9prl9igi3lWua7lUBxjFUP6nf8lYDW2kgaNlQ99kVFrgn8DvbktV4woGDwhjduGX za694O4YGa3CQMbm0t/Aw/frOgN/IYkRzM+oqXAT1BrGV6BqB9+60erjpi7mQKRRsSxhKP xhbjXgMz+kJYw4Do17+4ts2LQLNttuY919e9dflzk4jUsnMCiS7IPQMSrLWXTzLdIxWhZu wu+XDxvhzZ1h5r4cC1zoqJtSzUfygOGS82MrnLRgjvjnv58nJw92kUIioT3B35Qo8AAXg/ CdPFO4xZkyQuuczqfDV32+p5Ob/twwGxhHqz54qJoUneZjDPUmWOgPjKw85H/Q== To: u-boot@lists.denx.de Cc: Marek Vasut , Cheick Traore , Fabrice Gasnier , Gatien Chevallier , Lionel Debieve , Pascal Zimmermann , Patrice Chotard , Patrick Delaunay , Simon Glass , Sughosh Ganu , Tom Rini , u-boot@dh-electronics.com, uboot-stm32@st-md-mailman.stormreply.com Subject: [PATCH 04/10] ARM: stm32: Add STM32MP13xx PMIC initialization for DDR3 DRAM type Date: Mon, 12 May 2025 19:21:31 +0200 Message-ID: <20250512172149.150214-5-marek.vasut@mailbox.org> In-Reply-To: <20250512172149.150214-1-marek.vasut@mailbox.org> References: <20250512172149.150214-1-marek.vasut@mailbox.org> MIME-Version: 1.0 X-MBO-RS-ID: ee551b5348d262a5161 X-MBO-RS-META: swqn8niaunyarxayx3iotuteoggjj6jm X-Rspamd-Queue-Id: 4Zx5yP6h1Hz9smH X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The STM32MP13xx PMIC initialization for DDR3 DRAM type is similar to the STM32MP15xx PMIC initialization, except the VTT rail is not enabled. Fill in the STM32MP13xx support. Signed-off-by: Marek Vasut Reviewed-by: Patrice Chotard --- Cc: Cheick Traore Cc: Fabrice Gasnier Cc: Gatien Chevallier Cc: Lionel Debieve Cc: Pascal Zimmermann Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Simon Glass Cc: Sughosh Ganu Cc: Tom Rini Cc: u-boot@dh-electronics.com Cc: u-boot@lists.denx.de Cc: uboot-stm32@st-md-mailman.stormreply.com --- board/st/common/stpmic1.c | 51 ++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 17 deletions(-) diff --git a/board/st/common/stpmic1.c b/board/st/common/stpmic1.c index 45c2bb5bcea..b46f89dacb9 100644 --- a/board/st/common/stpmic1.c +++ b/board/st/common/stpmic1.c @@ -14,8 +14,19 @@ #include #include +static bool is_stm32mp13xx(void) +{ + if (!IS_ENABLED(CONFIG_STM32MP13X)) + return false; + + return of_machine_is_compatible("st,stm32mp131") || + of_machine_is_compatible("st,stm32mp133") || + of_machine_is_compatible("st,stm32mp135"); +} + int board_ddr_power_init(enum ddr_type ddr_type) { + bool is_mp13 = is_stm32mp13xx(); struct udevice *dev; bool buck3_at_1800000v = false; int ret; @@ -30,18 +41,21 @@ int board_ddr_power_init(enum ddr_type ddr_type) switch (ddr_type) { case STM32MP_DDR3: /* VTT = Set LDO3 to sync mode */ - ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); - if (ret < 0) - return ret; - - ret &= ~STPMIC1_LDO3_MODE; - ret &= ~STPMIC1_LDO12356_VOUT_MASK; - ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); - - ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - ret); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3)); + if (ret < 0) + return ret; + + ret &= ~STPMIC1_LDO3_MODE; + ret &= ~STPMIC1_LDO12356_VOUT_MASK; + ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL); + + ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + ret); + if (ret < 0) + return ret; + } /* VDD_DDR = Set BUCK2 to 1.35V */ ret = pmic_clrsetbits(dev, @@ -69,11 +83,14 @@ int board_ddr_power_init(enum ddr_type ddr_type) mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS); /* Enable VTT = LDO3 */ - ret = pmic_clrsetbits(dev, - STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), - STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); - if (ret < 0) - return ret; + if (!is_mp13) { + /* Enable VTT only on STM32MP15xx */ + ret = pmic_clrsetbits(dev, + STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3), + STPMIC1_LDO_ENA, STPMIC1_LDO_ENA); + if (ret < 0) + return ret; + } mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);