| Message ID | 20250511011003.15654-4-andre.przywara@arm.com |
|---|---|
| State | New |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | sunxi: Allwinner A133 SoC support | expand |
Hi Andre, On 5/11/25 3:10 AM, Andre Przywara wrote: > Add an Operating Performance Points table for the CPU cores to > enable Dynamic Voltage & Frequency Scaling on the A100. > > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com> > [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible] > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> > Link: https://patch.msgid.link/20241031070232.1793078-14-masterr3c0rd@epochal.quest > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > [ upstream commit: a8181e6861fec3068f393d77ff81b2aaf4ea4203 ] Did you use tools/update-subtree.sh to cherry-pick those commits? The changelog seems odd to me compared to what we usually get when using that tool. Modifications of dts/upstream should only be done via this tool. Same remark for the other DTS changes in this series. Cheers, Quentin
On Mon, 12 May 2025 11:24:07 +0200 Quentin Schulz <quentin.schulz@cherry.de> wrote: > Hi Andre, > > On 5/11/25 3:10 AM, Andre Przywara wrote: > > Add an Operating Performance Points table for the CPU cores to > > enable Dynamic Voltage & Frequency Scaling on the A100. > > > > Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com> > > [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible] > > Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> > > Link: https://patch.msgid.link/20241031070232.1793078-14-masterr3c0rd@epochal.quest > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > > > > [ upstream commit: a8181e6861fec3068f393d77ff81b2aaf4ea4203 ] > > Did you use tools/update-subtree.sh to cherry-pick those commits? The No, I didn't, just remembered that afterwards. This would only work for this patch anyways, since the other two DT patches are not yet merged in a tagged release (the last one isn't even reviewed yet), so I just added them here for completeness, to give people an idea of how the defconfig would look like and to allow compile testing. The plan was to maybe merge the first two patches (the DRAM code and Kconfig bits), then wait for the DT bits to trickle in. Thanks! Andre > changelog seems odd to me compared to what we usually get when using > that tool. Modifications of dts/upstream should only be done via this tool. > > Same remark for the other DTS changes in this series. > > Cheers, > Quentin
Hi Andre, On 5/12/25 12:46 PM, Andre Przywara wrote: > On Mon, 12 May 2025 11:24:07 +0200 > Quentin Schulz <quentin.schulz@cherry.de> wrote: > >> Hi Andre, >> >> On 5/11/25 3:10 AM, Andre Przywara wrote: >>> Add an Operating Performance Points table for the CPU cores to >>> enable Dynamic Voltage & Frequency Scaling on the A100. >>> >>> Signed-off-by: Shuosheng Huang <huangshuosheng@allwinnertech.com> >>> [masterr3c0rd@epochal.quest: fix typos in -cpu-opp, use compatible] >>> Signed-off-by: Cody Eksal <masterr3c0rd@epochal.quest> >>> Link: https://patch.msgid.link/20241031070232.1793078-14-masterr3c0rd@epochal.quest >>> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >>> >>> [ upstream commit: a8181e6861fec3068f393d77ff81b2aaf4ea4203 ] >> >> Did you use tools/update-subtree.sh to cherry-pick those commits? The > > No, I didn't, just remembered that afterwards. This would only work for > this patch anyways, since the other two DT patches are not yet merged in a > tagged release (the last one isn't even reviewed yet), so I just added them > here for completeness, to give people an idea of how the defconfig would > look like and to allow compile testing. > Considering you're the sunxi maintainer, I assume you wouldn't merge the patches knowing that they are not fitting the expected workflow so I'm not too worried :) > The plan was to maybe merge the first two patches (the DRAM code and > Kconfig bits), then wait for the DT bits to trickle in. > Sounds like a plan! Have fun :) Cheers, Quentin
diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts b/dts/upstream/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts index a387bccdcef..a7e3be0155a 100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts +++ b/dts/upstream/src/arm64/allwinner/sun50i-a100-allwinner-perf1.dts @@ -6,6 +6,7 @@ /dts-v1/; #include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -38,6 +39,10 @@ status = "okay"; }; +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + &pio { vcc-pb-supply = <®_dcdc1>; vcc-pc-supply = <®_eldo1>; diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi new file mode 100644 index 00000000000..c6a2efa037d --- /dev/null +++ b/dts/upstream/src/arm64/allwinner/sun50i-a100-cpu-opp.dtsi @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com> +// Copyright (c) 2020 ShuoSheng Huang <huangshuosheng@allwinnertech.com> + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "allwinner,sun50i-a100-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp-408000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <408000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-600000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <600000000>; + + opp-microvolt-speed0 = <900000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <940000>; + opp-microvolt-speed1 = <900000>; + opp-microvolt-speed2 = <900000>; + }; + + opp-1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1020000>; + opp-microvolt-speed1 = <980000>; + opp-microvolt-speed2 = <950000>; + }; + + opp-1200000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1200000000>; + + opp-microvolt-speed0 = <1100000>; + opp-microvolt-speed1 = <1020000>; + opp-microvolt-speed2 = <1000000>; + }; + + opp-1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1160000>; + opp-microvolt-speed1 = <1060000>; + opp-microvolt-speed2 = <1030000>; + }; + + opp-1464000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1464000000>; + + opp-microvolt-speed0 = <1180000>; + opp-microvolt-speed1 = <1180000>; + opp-microvolt-speed2 = <1130000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi index a24adba201a..f9f6fea03b7 100644 --- a/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi +++ b/dts/upstream/src/arm64/allwinner/sun50i-a100.dtsi @@ -23,6 +23,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu1: cpu@1 { @@ -30,6 +31,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu2: cpu@2 { @@ -37,6 +39,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; cpu3: cpu@3 { @@ -44,6 +47,7 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + clocks = <&ccu CLK_CPUX>; }; }; @@ -175,6 +179,10 @@ ths_calibration: calib@14 { reg = <0x14 8>; }; + + cpu_speed_grade: cpu-speed-grade@1c { + reg = <0x1c 0x2>; + }; }; watchdog@30090a0 {