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[v2] riscv: dts: jh7110: override syscrg assigned clock rates with defaults

Message ID 20250510184227.38768-1-e@freeshell.de
State Accepted
Commit bbf5f79bba07703c85ab9e3f4101758afb402c09
Delegated to: Andes
Headers show
Series [v2] riscv: dts: jh7110: override syscrg assigned clock rates with defaults | expand

Commit Message

E Shattow May 10, 2025, 6:42 p.m. UTC 
JH7110 drivers are missing support for CPU frequency scaling, so override
upstream device-tree to use default clock rates for syscrg. This override
duplicates a portion of jh7110-common-u-boot.dtsi file planned for removal.

Signed-off-by: E Shattow <e@freeshell.de>
Reviewed-by: Leo Liang <ycliang@andestech.com>
---
 arch/riscv/dts/jh7110-u-boot.dtsi | 1 +
 1 file changed, 1 insertion(+)


base-commit: feb55165233623648cb0a74953735b00ec6e322e
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Patch

diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index a9e318c4a31..4249fee3346 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -107,6 +107,7 @@ 
 };
 
 &syscrg {
+	assigned-clock-rates = <0>; /* cpufreq not implemented, use defaults */
 	bootph-pre-ram;
 };