| Message ID | 20250428044848.1132018-1-mchitale@ventanamicro.com |
|---|---|
| State | Accepted |
| Commit | fa317411ba564055d892e2b909112ca825449a42 |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: insn-def.h: Fix header guard | expand |
On Mon, Apr 28, 2025 at 04:48:45AM +0000, Mayuresh Chitale wrote: > Fix the erroneous header guard for insn-def.h to reflect the correct > header name. > > Fixes: bfc8ca3f7f6 ("riscv: Add support for defining instructions") > Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> > --- > arch/riscv/include/asm/insn-def.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 19a10cad84c..1869342b167 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -5,8 +5,8 @@ * Ported from linux insn-def.h. */ -#ifndef _ASM_RISCV_BARRIER_H -#define _ASM_RISCV_BARRIER_H +#ifndef _ASM_RISCV_INSN_DEF_H +#define _ASM_RISCV_INSN_DEF_H #define INSN_I_SIMM12_SHIFT 20 #define INSN_I_RS1_SHIFT 15 @@ -36,4 +36,4 @@ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \ RV_##rs1, RV_##simm12) -#endif /* _ASM_RISCV_BARRIER_H */ +#endif /* _ASM_RISCV_INSN_DEF_H */
Fix the erroneous header guard for insn-def.h to reflect the correct header name. Fixes: bfc8ca3f7f6 ("riscv: Add support for defining instructions") Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com> --- arch/riscv/include/asm/insn-def.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)