diff mbox series

[07/10] riscv: dts: th1520: Add DRAM controller

Message ID 20250426170059.35571-4-ziyao@disroot.org
State Superseded
Delegated to: Andes
Headers show
Series Initial SPL support for T-Head TH1520 SoC | expand

Commit Message

Yao Zi April 26, 2025, 5 p.m. UTC 
Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
devicetree blob.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/dts/th1520.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Leo Liang May 12, 2025, 6:04 p.m. UTC | #1 
On Sat, Apr 26, 2025 at 05:00:56PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL
> devicetree blob.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/dts/th1520.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index ef84d8cc265..b908eb37e41 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -372,6 +372,16 @@ 
 			status = "disabled";
 		};
 
+		ddrc: ddrc@fffd000000 {
+			compatible = "thead,th1520-ddrc";
+			reg = <0xff 0xfd000000 0x0 0x1000000>,
+			      <0xff 0xfe000000 0x0 0x1000000>,
+			      <0xff 0xff000000 0x0 0x4000>,
+			      <0xff 0xff005000 0x0 0x1000>;
+			reg-names = "phy-0", "phy-1", "ctrl", "sys";
+			bootph-pre-ram;
+		};
+
 		timer4: timer@ffffc33000 {
 			compatible = "snps,dw-apb-timer";
 			reg = <0xff 0xffc33000 0x0 0x14>;