| Message ID | 20250426170059.35571-3-ziyao@disroot.org |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Initial SPL support for T-Head TH1520 SoC | expand |
On Sat, Apr 26, 2025 at 05:00:55PM +0000, Yao Zi wrote: > [EXTERNAL MAIL] > > Memory node is necessary for TH1520 SPL to configure size and base > address of DRAM. Let's preserve it in SPL devicetree blob. > > Signed-off-by: Yao Zi <ziyao@disroot.org> > --- > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/arch/riscv/dts/th1520-lichee-module-4a.dtsi index 86a81bdcf77..20dbc4c7d24 100644 --- a/arch/riscv/dts/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi @@ -14,6 +14,7 @@ memory@0 { device_type = "memory"; reg = <0x0 0x00000000 0x2 0x00000000>; + bootph-pre-ram; }; };
Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi <ziyao@disroot.org> --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + 1 file changed, 1 insertion(+)