diff mbox series

[02/10] riscv: dts: th1520: Add clock-frequency for UART0

Message ID 20250426165704.35523-3-ziyao@disroot.org
State Superseded
Delegated to: Andes
Headers show
Series Initial SPL support for T-Head TH1520 SoC | expand

Commit Message

Yao Zi April 26, 2025, 4:56 p.m. UTC
The BROM of TH1520 always initializes its clock and configure the
baudrate to 115200. Add a clock-frequency property to provide such
information without introducing CCF to SPL.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/riscv/dts/th1520.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Leo Liang May 12, 2025, 9:57 a.m. UTC | #1
On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
> [EXTERNAL MAIL]
> 
> The BROM of TH1520 always initializes its clock and configure the
> baudrate to 115200. Add a clock-frequency property to provide such
> information without introducing CCF to SPL.
> 
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/riscv/dts/th1520.dtsi | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
E Shattow May 12, 2025, 11:53 a.m. UTC | #2
On 2025-05-12 05:57, Leo Liang wrote:
> On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
>> [EXTERNAL MAIL]
>> 
>> The BROM of TH1520 always initializes its clock and configure the
>> baudrate to 115200. Add a clock-frequency property to provide such
>> information without introducing CCF to SPL.
>> 
>> Signed-off-by: Yao Zi <ziyao@disroot.org>
>> ---
>>  arch/riscv/dts/th1520.dtsi | 1 +
>>  1 file changed, 1 insertion(+)
> 
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>

NAK from me. Quoting Emil "The uart0 node already has a reference to the 
uart0_core clock, so it shouldn't
need this property." If SPL does not support the clock framework to do 
this parent node lookup properly from device-tree then we should not be 
adjusting the device-tree in this way; use instead the codepath in 
serial driver that checks a compile-time define.

See for example: 
https://lore.kernel.org/u-boot/20250503115301.972550-1-e@freeshell.de/

- E
Yao Zi May 13, 2025, 4:06 a.m. UTC | #3
On Mon, May 12, 2025 at 07:53:01AM -0400, e wrote:
> On 2025-05-12 05:57, Leo Liang wrote:
> > On Sat, Apr 26, 2025 at 04:56:56PM +0000, Yao Zi wrote:
> > > [EXTERNAL MAIL]
> > > 
> > > The BROM of TH1520 always initializes its clock and configure the
> > > baudrate to 115200. Add a clock-frequency property to provide such
> > > information without introducing CCF to SPL.
> > > 
> > > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > > ---
> > >  arch/riscv/dts/th1520.dtsi | 1 +
> > >  1 file changed, 1 insertion(+)
> > 
> > Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> 
> NAK from me. Quoting Emil "The uart0 node already has a reference to the
> uart0_core clock, so it shouldn't
> need this property." If SPL does not support the clock framework to do this
> parent node lookup properly from device-tree then we should not be adjusting
> the device-tree in this way; use instead the codepath in serial driver that
> checks a compile-time define.

I was not aware of the codepath, thanks for the hint! It should be the
correct way to go and I'll try to take in v2.

> See for example:
> https://lore.kernel.org/u-boot/20250503115301.972550-1-e@freeshell.de/
> 
> - E

Best regards,
Yao Zi
diff mbox series

Patch

diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi
index cbe3481fadd..e4c8cee66bc 100644
--- a/arch/riscv/dts/th1520.dtsi
+++ b/arch/riscv/dts/th1520.dtsi
@@ -175,6 +175,7 @@ 
 			reg = <0xff 0xe7014000 0x0 0x100>;
 			interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&uart_sclk>;
+			clock-frequency = <100000000>;
 			reg-shift = <2>;
 			reg-io-width = <4>;
 			status = "disabled";