| Message ID | 20250426165704.35523-2-ziyao@disroot.org |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | Initial SPL support for T-Head TH1520 SoC | expand |
On Sat, Apr 26, 2025 at 04:56:55PM +0000, Yao Zi wrote: > [EXTERNAL MAIL] > > Designed before a standard set of cache management operations defined in > RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the > customized extension XTheadCMO, which has been used in the CV1800B port > of U-Boot. > > This patch splits XTheadCMO-related code into a generic module, allowing > SoCs shipping T-Head cores to share the code. > > Link: https://github.com/XUANTIE-RV/thead-extension-spec > Signed-off-by: Yao Zi <ziyao@disroot.org> > --- > arch/riscv/Kconfig | 8 ++++++++ > arch/riscv/cpu/cv1800b/Kconfig | 1 + > arch/riscv/cpu/cv1800b/Makefile | 1 - > arch/riscv/lib/Makefile | 1 + > arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0 > 5 files changed, 10 insertions(+), 1 deletion(-) > rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%) Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b24623590f2..dc36d9b8566 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -77,6 +77,14 @@ config SYS_DCACHE_OFF help Do not enable data cache in U-Boot. +config SYS_CACHE_THEAD_CMO + bool "THEAD non-standard cache operations" + depends on !SYS_DCACHE_OFF + default n + help + Support for non-standard cache management operations on SoCs based on + T-Head C906/C910 cores. + config SPL_SYS_DCACHE_OFF bool "Do not enable dcache in SPL" depends on SPL diff --git a/arch/riscv/cpu/cv1800b/Kconfig b/arch/riscv/cpu/cv1800b/Kconfig index 7225b1210c5..57f724ae043 100644 --- a/arch/riscv/cpu/cv1800b/Kconfig +++ b/arch/riscv/cpu/cv1800b/Kconfig @@ -6,6 +6,7 @@ config SOPHGO_CV1800B bool select ARCH_EARLY_INIT_R select SYS_CACHE_SHIFT_6 + select SYS_CACHE_THEAD_CMO imply CPU imply CPU_RISCV imply RISCV_TIMER diff --git a/arch/riscv/cpu/cv1800b/Makefile b/arch/riscv/cpu/cv1800b/Makefile index 95beb34b51a..da12e0f64e1 100644 --- a/arch/riscv/cpu/cv1800b/Makefile +++ b/arch/riscv/cpu/cv1800b/Makefile @@ -4,4 +4,3 @@ obj-y += dram.o obj-y += cpu.o -obj-y += cache.o diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 189b35c24d3..db8d235c699 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_GO) += boot.o obj-y += cache.o obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o +obj-$(CONFIG_SYS_CACHE_THEAD_CMO) += thead_cmo.o ifeq ($(CONFIG_$(PHASE_)RISCV_MMODE),y) obj-$(CONFIG_$(PHASE_)RISCV_ACLINT) += aclint_ipi.o obj-$(CONFIG_ANDES_PLICSW) += andes_plicsw.o diff --git a/arch/riscv/cpu/cv1800b/cache.c b/arch/riscv/lib/thead_cmo.c similarity index 100% rename from arch/riscv/cpu/cv1800b/cache.c rename to arch/riscv/lib/thead_cmo.c
Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowing SoCs shipping T-Head cores to share the code. Link: https://github.com/XUANTIE-RV/thead-extension-spec Signed-off-by: Yao Zi <ziyao@disroot.org> --- arch/riscv/Kconfig | 8 ++++++++ arch/riscv/cpu/cv1800b/Kconfig | 1 + arch/riscv/cpu/cv1800b/Makefile | 1 - arch/riscv/lib/Makefile | 1 + arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} | 0 5 files changed, 10 insertions(+), 1 deletion(-) rename arch/riscv/{cpu/cv1800b/cache.c => lib/thead_cmo.c} (100%)