diff mbox series

[v6,02/11] riscv: dts: jh7110: Make u-boot device trees adapting to upstream DT

Message ID 20241125003205.75327-3-hal.feng@starfivetech.com
State Superseded
Delegated to: Andes
Headers show
Series Support OF_UPSTREAM for StarFive JH7110 | expand

Commit Message

Hal Feng Nov. 25, 2024, 12:31 a.m. UTC 
Add u-boot features to the U-Boot device tree.

Tested-by: E Shattow <lucent@gmail.com>
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
 ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 35 ++++++++++++++++---
 arch/riscv/dts/jh7110-u-boot.dtsi             | 34 ++++++++++++++++++
 2 files changed, 65 insertions(+), 4 deletions(-)

Comments

E Shattow Nov. 26, 2024, 3:14 p.m. UTC | #1 
On Sun, Nov 24, 2024 at 4:33 PM Hal Feng <hal.feng@starfivetech.com> wrote:
>
> Add u-boot features to the U-Boot device tree.
>
> Tested-by: E Shattow <lucent@gmail.com>
> Acked-by: Sumit Garg <sumit.garg@linaro.org>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
>  ...10-starfive-visionfive-2-v1.3b-u-boot.dtsi | 35 ++++++++++++++++---
>  arch/riscv/dts/jh7110-u-boot.dtsi             | 34 ++++++++++++++++++
>  2 files changed, 65 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> index 3012466b30..c44553455e 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
> @@ -6,6 +6,10 @@
>  #include "binman.dtsi"
>  #include "jh7110-u-boot.dtsi"
>  / {
> +       aliases {
> +               spi0 = &qspi;
> +       };
> +
>         chosen {
>                 bootph-pre-ram;
>         };
> @@ -27,42 +31,62 @@
>
>  &uart0 {
>         bootph-pre-ram;
> +       reg-offset = <0>;
> +       current-speed = <115200>;
> +       clock-frequency = <24000000>;
>  };
>
>  &mmc0 {
>         bootph-pre-ram;
> +       compatible = "snps,dw-mshc";
>  };
>
>  &mmc1 {
>         bootph-pre-ram;
> +       compatible = "snps,dw-mshc";
>  };
>
>  &qspi {
>         bootph-pre-ram;
> +       spi-max-frequency = <250000000>;
>
> -       nor-flash@0 {
> +       flash@0 {
>                 bootph-pre-ram;
> +               /delete-property/ cdns,read-delay;
> +               spi-max-frequency = <100000000>;
>         };
>  };
>
> +&syscrg {
> +       assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
> +                         <&syscrg JH7110_SYSCLK_BUS_ROOT>,
> +                         <&syscrg JH7110_SYSCLK_PERH_ROOT>,
> +                         <&syscrg JH7110_SYSCLK_QSPI_REF>;
> +       assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
> +                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +                                <&pllclk JH7110_PLLCLK_PLL2_OUT>,
> +                                <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
> +       assigned-clock-rates = <0>, <0>, <0>, <0>;
> +};
> +
>  &sysgpio {
>         bootph-pre-ram;
>  };
>
>  &mmc0_pins {
>         bootph-pre-ram;
> -       mmc0-pins-rest {
> +       rst-pins {
>                 bootph-pre-ram;
>         };
>  };
>
>  &mmc1_pins {
>         bootph-pre-ram;
> -       mmc1-pins0 {
> +       clk-pins {
>                 bootph-pre-ram;
>         };
>
> -       mmc1-pins1 {
> +       mmc-pins {
>                 bootph-pre-ram;
>         };
>  };

> @@ -78,6 +102,9 @@
>         bootph-pre-ram;
>         eeprom@50 {
>                 bootph-pre-ram;
> +               compatible = "atmel,24c04";
> +               reg = <0x50>;
> +               pagesize = <16>;
>         };
>  };

In some configurations with RTC there is a conflict in the addressing
with EEPROM, as in:

https://github.com/milkv-mars/mars-buildroot-sdk/commit/d381610c92827de01b25843786012351b3f35519

Okay to keep this for now, a conflict is the exception and not the
normal situation. Refactor this out of U-Boot when EEPROM node is sent
upstream to Linux.

>
> diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
> index 52c1d60859..21a2ab1789 100644
> --- a/arch/riscv/dts/jh7110-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-u-boot.dtsi
> @@ -46,6 +46,15 @@
>                 };
>         };
>
> +       timer {
> +               compatible = "riscv,timer";
> +               interrupts-extended = <&cpu0_intc 5>,
> +                                     <&cpu1_intc 5>,
> +                                     <&cpu2_intc 5>,
> +                                     <&cpu3_intc 5>,
> +                                     <&cpu4_intc 5>;
> +       };
> +
>         soc {
>                 bootph-pre-ram;
>
> @@ -73,10 +82,35 @@
>         bootph-pre-ram;
>  };
>
> +&gmac0_rgmii_rxin {
> +       bootph-pre-ram;
> +};
> +
>  &gmac0_rmii_refin {
>         bootph-pre-ram;
>  };
>
> +&gmac1_rgmii_rxin {
> +       bootph-pre-ram;
> +};
> +
> +&gmac1_rmii_refin {
> +       bootph-pre-ram;
> +};
> +
> +&stmmac_axi_setup {
> +       snps,wr_osr_lmt = <4>;
> +       snps,rd_osr_lmt = <4>;
> +};
> +
> +&gmac0 {
> +       snps,perfect-filter-entries = <8>;
> +};
> +
> +&gmac1 {
> +       snps,perfect-filter-entries = <8>;
> +};
> +
>  &aoncrg {
>         bootph-pre-ram;
>  };
> --
> 2.43.2
>

Reviewed-by: E Shattow <lucent@gmail.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
index 3012466b30..c44553455e 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-v1.3b-u-boot.dtsi
@@ -6,6 +6,10 @@ 
 #include "binman.dtsi"
 #include "jh7110-u-boot.dtsi"
 / {
+	aliases {
+		spi0 = &qspi;
+	};
+
 	chosen {
 		bootph-pre-ram;
 	};
@@ -27,42 +31,62 @@ 
 
 &uart0 {
 	bootph-pre-ram;
+	reg-offset = <0>;
+	current-speed = <115200>;
+	clock-frequency = <24000000>;
 };
 
 &mmc0 {
 	bootph-pre-ram;
+	compatible = "snps,dw-mshc";
 };
 
 &mmc1 {
 	bootph-pre-ram;
+	compatible = "snps,dw-mshc";
 };
 
 &qspi {
 	bootph-pre-ram;
+	spi-max-frequency = <250000000>;
 
-	nor-flash@0 {
+	flash@0 {
 		bootph-pre-ram;
+		/delete-property/ cdns,read-delay;
+		spi-max-frequency = <100000000>;
 	};
 };
 
+&syscrg {
+	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
+			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
+			  <&syscrg JH7110_SYSCLK_PERH_ROOT>,
+			  <&syscrg JH7110_SYSCLK_QSPI_REF>;
+	assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
+				 <&syscrg JH7110_SYSCLK_QSPI_REF_SRC>;
+	assigned-clock-rates = <0>, <0>, <0>, <0>;
+};
+
 &sysgpio {
 	bootph-pre-ram;
 };
 
 &mmc0_pins {
 	bootph-pre-ram;
-	mmc0-pins-rest {
+	rst-pins {
 		bootph-pre-ram;
 	};
 };
 
 &mmc1_pins {
 	bootph-pre-ram;
-	mmc1-pins0 {
+	clk-pins {
 		bootph-pre-ram;
 	};
 
-	mmc1-pins1 {
+	mmc-pins {
 		bootph-pre-ram;
 	};
 };
@@ -78,6 +102,9 @@ 
 	bootph-pre-ram;
 	eeprom@50 {
 		bootph-pre-ram;
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
 	};
 };
 
diff --git a/arch/riscv/dts/jh7110-u-boot.dtsi b/arch/riscv/dts/jh7110-u-boot.dtsi
index 52c1d60859..21a2ab1789 100644
--- a/arch/riscv/dts/jh7110-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-u-boot.dtsi
@@ -46,6 +46,15 @@ 
 		};
 	};
 
+	timer {
+		compatible = "riscv,timer";
+		interrupts-extended = <&cpu0_intc 5>,
+				      <&cpu1_intc 5>,
+				      <&cpu2_intc 5>,
+				      <&cpu3_intc 5>,
+				      <&cpu4_intc 5>;
+	};
+
 	soc {
 		bootph-pre-ram;
 
@@ -73,10 +82,35 @@ 
 	bootph-pre-ram;
 };
 
+&gmac0_rgmii_rxin {
+	bootph-pre-ram;
+};
+
 &gmac0_rmii_refin {
 	bootph-pre-ram;
 };
 
+&gmac1_rgmii_rxin {
+	bootph-pre-ram;
+};
+
+&gmac1_rmii_refin {
+	bootph-pre-ram;
+};
+
+&stmmac_axi_setup {
+	snps,wr_osr_lmt = <4>;
+	snps,rd_osr_lmt = <4>;
+};
+
+&gmac0 {
+	snps,perfect-filter-entries = <8>;
+};
+
+&gmac1 {
+	snps,perfect-filter-entries = <8>;
+};
+
 &aoncrg {
 	bootph-pre-ram;
 };