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[v2,1/8] riscv: Make A ISA extension selectable

Message ID 20240910093920.1142455-2-chiawei_wang@aspeedtech.com
State Accepted
Commit 9c0ed7214298e4d9e575bff0f34ae6cacba8bfc4
Delegated to: Andes
Headers show
Series riscv: Add AST2700 platform support | expand

Commit Message

ChiaWei Wang Sept. 10, 2024, 9:39 a.m. UTC 
Make the Atomic (A) ISA extension selectable. Thus CPUs such as
Ibex without the A extension can be supported.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
 arch/riscv/Kconfig | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
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Patch

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa3b016c527..c5859c5c541 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -308,7 +308,10 @@  config TPL_USE_ARCH_STRNCMP
 endmenu
 
 config RISCV_ISA_A
-	def_bool y
+	bool "Standard extension for Atomic Instructions"
+	default y
+	help
+	  Adds "A" to the ISA string passed to the compiler.
 
 config DMA_ADDR_T_64BIT
 	bool