| Message ID | 20240528125750.947283-1-ycliang@andestech.com |
|---|---|
| State | Accepted |
| Commit | 1d29c718b7ba09807f8060796d9c21772e3c1b52 |
| Delegated to: | Andes |
| Headers | show |
| Series | [v2,1/1] andes: Use UCCTLCOMMAND instead of MCCTLCOMMAND | expand |
diff --git a/arch/riscv/cpu/andes/cache.c b/arch/riscv/cpu/andes/cache.c index 7d3df8722d..bb57498d75 100644 --- a/arch/riscv/cpu/andes/cache.c +++ b/arch/riscv/cpu/andes/cache.c @@ -43,9 +43,7 @@ static void cache_ops(int (*ops)(struct udevice *dev)) void flush_dcache_all(void) { -#if CONFIG_IS_ENABLED(RISCV_MMODE) - csr_write(CSR_MCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); -#endif + csr_write(CSR_UCCTLCOMMAND, CCTL_L1D_WBINVAL_ALL); } void flush_dcache_range(unsigned long start, unsigned long end) diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 028fd01c2f..7d6104a24e 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -12,7 +12,7 @@ #define CSR_MCACHE_CTL 0x7ca #define CSR_MMISC_CTL 0x7d0 -#define CSR_MCCTLCOMMAND 0x7cc +#define CSR_UCCTLCOMMAND 0x80c /* mcache_ctl register */
Use CSR_UCCTLCOMMAND instead of CSR_MCCTLCOMMAND to do cache flush operation in M-mode and S-mode. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> --- arch/riscv/cpu/andes/cache.c | 4 +--- arch/riscv/include/asm/arch-andes/csr.h | 2 +- 2 files changed, 2 insertions(+), 4 deletions(-)